Abstract: A bus circuit capable of realizing a high speed data transfer cycle by eliminating undesired voltage amplitude of the data bus lines, includes a plurality of data bus lines, a potential initializing circuit for setting the initial potential of these data bus lines, an output port circuit for delivering data to these data bus lines, and an input port circuit for feeding data from these data bus lines. At least one of the data bus lines is a potential sensing line, and the sensing line is coupled to an inverting output circuit for inverting the initial potential from the output port circuit, and the potential change of this inverting output means is detected by a data firm judging means connected to the sensing line, and the output port circuit is deactivated by a control circuit in accordance with a judgement signal from the data firm judging circuit.

Abstract: Method for measuring power supply current, e.g., standby current of a random access memory in which, before starting measurement of the power supply current, data is read-out from memory cell of the random access memory and opposite data is written in the memory cell so that the random access memory enters into an unstabilized state. By use of this method, the measurement of the maximum power supply current can be conducted precisely.

Abstract: In a C MOS IC as shown in FIG. 7(A) and FIG. 8, the IC comprises vertical row of horizontally long blocks, each block comprising p-type MOS transistor region and n-type MOS transistor region, the IC comprises horizontal wirings of aluminum (31, 32, 33) and vertical wirings of polycrystalline silicon (61, 62, 63, 64, 65, 41, 42), with insulation films on the upper side and on the lower side of the polycrystalline silicon film, between the rows (I, II, . . .), said horizontal aluminum wirings (31, 32, 33) and said polycrystalline silicon wiring (61, 62 . . ., 41, 42) being appropriately connected through openings (105, 105 . . .) formed in said insulation film inbetween, said vertical polycrystalline silicon wirings being connected through aluminum wirings in said blocks.

Abstract: The static random access memory reduces the access time thereof and reduces the power consumption thereof during its time of operation, and employs a circuit arrangement such that not only is the logical amplitude of each bit line diminished during a read-out operation, but the bit line is precharged after a write operation is accomplished during a write operation.

Abstract: A CMOS integrated circuit includes a P-channel type MOS transistor which is formed on an N-type silicon substrate, an N-channel type MOS transistor which is formed on a P well formed in the substrate, and parasitic bipolar transistors which are electrically connected to each other to form a kind of thyristor structure. A power supply voltage is applied to a source electrode of the P-channel type MOS transistor through a part of the substrate which presents a resistance. The resistance is electrically connected to the parasitic bipolar transistor of the thyristor structure to thereby prevent the occurrence of a latch-up phenomenon in which a large current continuously flows through the parasitic bipolar transistors and may destroy the CMOS integrated circuit. Because of the prevention of the latch-up phenomenon, the CMOS integrated circuit is always maintained in good condition.

Abstract: An associative memory comprises memory cells arrayed in columns and rows, a pair of complementary bit lines disposed for each column of the memory cells, a word line disposed for each row of the memory cells, and a sense line disposed also for each row of the memory cells. Each memory cell includes a bistable circuit provided by a pair of cross-coupled inverters, a pair of first switching elements connected between the two nodal points of the bistable circuit and the bit lines respectively to be controlled depending on the potential of the word line, and a pair of second switching elements and a pair of diodes or like circuit elements having a rectifying characteristic connected in series between the bit lines and the sense line respectively. These second switching elements are controlled depending on the potentials of the two nodal points respectively in the bistable circuit. A load element, a sensing amplifier and a tri-state driver circuit are connected to the sense line.

Abstract: This invention provides a method of making an improved gate structure in which the gate electrode is self-aligned with respect to the field isolation oxide regions.Gate constituting layers are formed on a substrate prior to formation of the field isolation oxide regions. An oxidation barrier layer is provided on such layers, also covering the other regions which should be formed into the source and drain regions, etc. By etching off the oxidation barrier layer above the field isolation regions, the boundary edges of the gate on the field isolation regions are formed. Then oxidation is performed using the oxidation barrier as a masking pattern to form the field isolation oxide regions. The field isolation oxide regions and the gate thus formed completely coincide with each other at their boundary edges.

Abstract: A semiconductor device is described comprising a semiconductor substrate, plural impurity-diffused regions formed in the substrate, an insulation layer formed so as to cover selected parts of the substrate, plural low-resistance semiconductor regions isolated from each other by the insulation layer and at least some of them contacting said diffused regions and conductive regions disposed in a manner to contact said low-resistance semiconductor regions, respectively.Thus, the low-resistance semiconductor regions serve as connection means between the diffused region and the conductive region, which means serves to uniform contacting level, thereby decreasing the size of the device.