Abstract: Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction.

Abstract: Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction.

Abstract: Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction.

Abstract: Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction.

Abstract: A semiconductor device with a low drain current in the off-state of LDD type accommodating high voltages is provided. On the thermal oxide film, a polysilicon film and a CVD oxide film, and a resist pattern are formed, then the CVD oxide film is side-etched for formation of a CVD oxide film which is after the etching one-size smaller than the polysilicon film. Using the resist pattern as a mask, an impurity is implanted at a high concentration for formation of a source/drain region at a high concentration in an area which does not overlap with the polysilicon film. Further, the resist pattern is removed, and using the CVD oxide film as a mask, an impurity is implanted at a low concentration for formation of an LDD region of a low concentration in an area which overlaps with the gate electrode of the polysilicon film.

Abstract: A semiconductor device with a low drain current in the off-state of LDD type accommodating high voltages is provided. On the thermal oxide film, a polysilicon film and a CVD oxide film, and a resist pattern are formed, then the CVD oxide film is side-etched for formation of a CVD oxide film which is after the etching one-size smaller than the polysilicon film. Using the resist pattern as a mask, an impurity is implanted at a high concentration for formation of a source/drain region at a high concentration in an area which does not overlap with the polysilicon film. Further, the resist pattern is removed, and using the CVD oxide film as a mask, an impurity is implanted at a low concentration for formation of an LDD region of a low concentration in an area which overlaps with the gate electrode of the polysilicon film.