Patents by Inventor Eisuke Tokumitsu

Eisuke Tokumitsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240250145
    Abstract: A ferroelectric film that includes: hafnium oxide having a fluorite structure; a metal oxide having one or more elements selected from La, Ce and Bi; and less than 5 mol % of carbon, wherein the ferroelectric film is a polycrystalline body having an average particle size of less than 10 nm.
    Type: Application
    Filed: February 22, 2024
    Publication date: July 25, 2024
    Inventors: Shingo YONEDA, Takaaki MIYASAKO, Tadasu HOSOKURA, Eisuke TOKUMITSU
  • Publication number: 20230246040
    Abstract: A variable capacitive element is provided that includes a switch configuring a field effect transistor, and an element that is electrically connected to the switch to configure a capacitor. The element includes a terminal electrode electrically connected to a source electrode, and a terminal electrode that configures a first capacitor with the source electrode and configures a second capacitor at least with the drain electrode.
    Type: Application
    Filed: April 11, 2023
    Publication date: August 3, 2023
    Inventors: Takaaki MIYASAKO, Eisuke TOKUMITSU
  • Patent number: 9876067
    Abstract: The invention provides a dielectric layer having high relative permittivity with low leakage current and excellent flatness. A dielectric layer 30a according to the invention is made of multilayer oxide including a first oxide layer 31 made of oxide consisting of bismuth (Bi) and niobium (Nb) or oxide consisting of bismuth (Bi), zinc (Zn), and niobium (Nb) (possibly including inevitable impurities) and a second oxide layer 32 made of oxide of one type (possibly including inevitable impurities) selected from the group of oxide consisting of lanthanum (La) and tantalum (Ta), oxide consisting of lanthanum (La) and zirconium (Zr), and oxide consisting of strontium (Sr) and tantalum (Ta).
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: January 23, 2018
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Tatsuya Shimoda, Eisuke Tokumitsu, Masatoshi Onoue, Takaaki Miyasako
  • Publication number: 20160284790
    Abstract: The invention provides a dielectric layer having high relative permittivity with low leakage current and excellent flatness. A dielectric layer 30a according to the invention is made of multilayer oxide including a first oxide layer 31 made of oxide consisting of bismuth (Bi) and niobium (Nb) or oxide consisting of bismuth (Bi), zinc (Zn), and niobium (Nb) (possibly including inevitable impurities) and a second oxide layer 32 made of oxide of one type (possibly including inevitable impurities) selected from the group of oxide consisting of lanthanum (La) and tantalum (Ta), oxide consisting of lanthanum (La) and zirconium (Zr), and oxide consisting of strontium (Sr) and tantalum (Ta).
    Type: Application
    Filed: March 12, 2014
    Publication date: September 29, 2016
    Inventors: Tatsuya SHIMODA, Eisuke TOKUMITSU, Masatoshi ONOUE, Takaaki MIYASAKO
  • Patent number: 9293257
    Abstract: A solid-state electronic device according to the present invention includes: an oxide layer (possibly containing inevitable impurities) that is formed by heating, in an atmosphere containing oxygen, a precursor layer obtained from a precursor solution as a start material including both a precursor containing bismuth (Bi) and a precursor containing niobium (Nb) as solutes, the oxide layer consisting of the bismuth (Bi) and the niobium (Nb); wherein the oxide layer is formed by heating at a heating temperature from 520° C. to 650° C.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 22, 2016
    Assignee: Japan Science and Technology Agency
    Inventors: Tatsuya Shimoda, Eisuke Tokumitsu, Masatoshi Onoue, Takaaki Miyasako
  • Publication number: 20160016813
    Abstract: An oxide layer 30 according to the invention consists of bismuth (Bi) and niobium (Nb) (possibly including inevitable impurities). The oxide layer 30 also includes crystal phases of a pyrochlore crystal structure. The obtained oxide layer 30 includes oxide consisting of bismuth (Bi) and niobium (Nb) and has high permittivity that has never been achieved in the conventional technique.
    Type: Application
    Filed: January 6, 2014
    Publication date: January 21, 2016
    Inventors: Tatsuya SHIMODA, Eisuke TOKUMITSU, Masatoshi ONOUE, Takaaki MIYASAKO
  • Patent number: 9202895
    Abstract: A method of producing a functional device according to the present invention includes, in this order: the functional solid material precursor layer formation step of applying a functional liquid material onto a base material to form a precursor layer of a functional solid material; the drying step of heating the precursor layer to a first temperature in a range from 80° C. to 250° C. to preliminarily decrease fluidity of the precursor layer; the imprinting step of imprinting the precursor layer that is heated to a second temperature in a range from 80° C. to 300° C. to form an imprinted structure on the precursor layer; and the functional solid material layer formation step of heat treating the precursor layer at a third temperature higher than the second temperature to transform the precursor layer into a functional solid material layer.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: December 1, 2015
    Assignee: Japan Science and Technology Agency
    Inventors: Tatsuya Shimoda, Eisuke Tokumitsu, Takaaki Miyasako, Toshihiko Kaneda
  • Patent number: 9123752
    Abstract: A method of producing a functional device according to the present invention includes, in this order: the functional solid material precursor layer formation step of applying a functional liquid material onto a base material to form a precursor layer of a functional solid material; the drying step of heating the precursor layer to a first temperature in a range from 80° C. to 250° C. to preliminarily decrease fluidity of the precursor layer; the imprinting step of imprinting the precursor layer that is heated to a second temperature in a range from 80° C. to 300° C. to form an imprinted structure on the precursor layer; and the functional solid material layer formation step of heat treating the precursor layer at a third temperature higher than the second temperature to transform the precursor layer into a functional solid material layer.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: September 1, 2015
    Assignee: Japan Science and Technology Agency
    Inventors: Tatsuya Shimoda, Eisuke Tokumitsu, Takaaki Miyasako, Toshihiko Kaneda
  • Publication number: 20150093841
    Abstract: A method of producing a functional device according to the present invention includes, in this order: the functional solid material precursor layer formation step of applying a functional liquid material onto a base material to form a precursor layer of a functional solid material; the drying step of heating the precursor layer to a first temperature in a range from 80° C. to 250° C. to preliminarily decrease fluidity of the precursor layer; the imprinting step of imprinting the precursor layer that is heated to a second temperature in a range from 80° C. to 300° C. to form an imprinted structure on the precursor layer; and the functional solid material layer formation step of heat treating the precursor layer at a third temperature higher than the second temperature to transform the precursor layer into a functional solid material layer.
    Type: Application
    Filed: November 3, 2014
    Publication date: April 2, 2015
    Inventors: Tatsuya SHIMODA, Eisuke TOKUMITSU, Takaaki MIYASAKO, Toshihiko KANEDA
  • Publication number: 20140339550
    Abstract: Provided is a ferroelectric gate thin film transistor which includes: a channel layer; a gate electrode layer which controls a conductive state of the channel layer; and a gate insulation layer which is arranged between the channel layer and the gate electrode layer and is formed of a ferroelectric layer. The gate insulation layer (ferroelectric layer) has the structure where a PZT layer and a BLT layer (Pb diffusion preventing layer) are laminated to each other. The channel layer (oxide conductor layer) is arranged on a surface of the gate insulation layer (ferroelectric layer) on a BLT layer (Pb diffusion preventing layer) side. The ferroelectric gate thin film transistor can overcome various drawbacks which may be caused due to the diffusion of Pb atoms into an oxide conductor layer from a PZT layer including a drawback that a transmission characteristic of a ferroelectric gate thin film transistor is liable to be deteriorated (for example, a width of a memory window is liable to become narrow).
    Type: Application
    Filed: October 23, 2012
    Publication date: November 20, 2014
    Inventors: Tatsuya Shimoda, Takaaki Miyasako, Eisuke Tokumitsu, Bui Nguyen Quoc Trinh
  • Publication number: 20140319660
    Abstract: A solid-state electronic device according to the present invention includes: an oxide layer (possibly containing inevitable impurities) that is formed by heating, in an atmosphere containing oxygen, a precursor layer obtained from a precursor solution as a start material including both a precursor containing bismuth (Bi) and a precursor containing niobium (Nb) as solutes, the oxide layer consisting of the bismuth (Bi) and the niobium (Nb); wherein the oxide layer is formed by heating at a heating temperature from 520° C. to 650° C.
    Type: Application
    Filed: October 25, 2012
    Publication date: October 30, 2014
    Inventors: Tatsuya Shimoda, Eisuke Tokumitsu, Masatoshi Onoue, Takaaki Miyasako
  • Publication number: 20130240871
    Abstract: A method of producing a functional device according to the present invention includes, in this order: the functional solid material precursor layer formation step of applying a functional liquid material onto a base material to form a precursor layer of a functional solid material; the drying step of heating the precursor layer to a first temperature in a range from 80° C. to 250° C. to preliminarily decrease fluidity of the precursor layer; the imprinting step of imprinting the precursor layer that is heated to a second temperature in a range from 80° C. to 300° C. to form an imprinted structure on the precursor layer; and the functional solid material layer formation step of heat treating the precursor layer at a third temperature higher than the second temperature to transform the precursor layer into a functional solid material layer.
    Type: Application
    Filed: May 6, 2011
    Publication date: September 19, 2013
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Tatsuya Shimoda, Eisuke Tokumitsu, Takaaki Miyasako, Toshihiko Kaneda
  • Patent number: 5822239
    Abstract: The invention is directed to a writing method to effectively suppress inter-cell interference when writing data to a single transistor type ferroelectric memory. When V is a writing voltage, stripe-like conducting electrodes are row electrodes, and semiconductor stripes are column electrodes, then the writing method includes a first procedure and a successive second procedure based on V/3 rule. In the first procedure, when a voltage of +V is applied to the row electrode of the cell being observed, while a voltage of zero is applied to the column electrode, and voltages of +V/3 are applied to the other row electrodes, and voltages of +(2/3)V are applied to the other column electrodes, then in the second procedure, a voltage of zero is applied to the row electrode of the cell being observed, while a voltage of +V/3 is applied to the column electrode, and voltages of +V/3 are applied to the other row electrodes, and voltages of zero are applied to the other column electrodes.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: October 13, 1998
    Assignee: Tokyo Institute of Technology
    Inventors: Hiroshi Ishihara, Eisuke Tokumitsu