Abstract: A high gain clock circuit that includes an input section that receives an input clock on an input section input. A self terminating pre-charge section is connected to the input section and includes domino logic. An output section is connected to the self terminating pre-charge section and produces an output clock at an output section output. The clock circuit encompasses a small area and achieves high gain at the output section output relative to the input section input. The high gain clock circuit has higher gain than known circuits and is characterized by fast rise time and slower fall time.

Abstract: A high gain clock circuit that includes an input section that receives an input clock on an input section input. A self terminating pre-charge section is connected to the input section and includes domino logic. An output section is connected to the self terminating pre-charge section and produces an output clock at an output section output. The clock circuit encompasses a small area and achieves high gain at the output section output relative to the input section input. The high gain clock circuit has higher gain than known circuits and is characterized by fast rise time and slower fall time.

Abstract: A high gain clock circuit that includes an input section that receives an input clock on an input section input. A self terminating pre-charge section is connected to the input section and includes domino logic. An output section is connected to the self terminating pre-charge section and produces an output clock at an output section output. The clock circuit encompasses a small area and achieves high gain at the output section output relative to the input section input. The high gain clock circuit has higher gain than known circuits and is characterized by fast rise time and slower fall time.

Abstract: A control circuit for clock enable staging between first and second clock macros wherein each clock macro produces a clock signal at an output in response to a transition of a global clock signal when an enable signal has been activated. The control circuit comprises a latch element having a first input coupled to the output of the first clock macro, a second input of the latch element is coupled to the output of the second clock macro, and an output node coupled to the enable input of the second clock macro. The output node of the latch element activates the enable input of the second clock macro responsive to the clock signal at the output of the first clock macro, and inactivates the enable input of the second clock macro responsive to the clock signal at the output of the second clock macro.

Abstract: A fast, fully associative translation lookaside buffer (TLB) with the ability to store and manage information pertaining to at least two different page sizes is disclosed. The TLB utilizes a tag array with tag lines and a data array with corresponding data lines. Within the tag array, each tag line incorporates a control cell which selectively enables or disables comparisons of tag bits to corresponding bits from an input address to the TLB. Within the data array, each data line incorporates control cells and multiplexing data cells to selectively determine whether bits in the physical address output of the TLB will be the derived from of the contents of the multiplexing data cells or bits from the input address. The use of control cells in the tag array and control cells and multiplexing data cells in the data array thereby provides for the ability to store and manage information pertaining to at least two different page sizes in a single TLB.

Abstract: A fast, fully associative translation lookaside buffer (TLB) with the ability to store and manage information pertaining to at least two different page sizes is described. The TLB utilizes a tag array with tag lines and a data array with corresponding data lines. Within the tag array, each tag line incorporates a control cell which selectively enables or disables comparisons of tag bits to corresponding bits from an input address to the TLB. Within the data array, each data line incorporates control cells and multiplexing data cells to selectively determine whether bits in the physical address output of the TLB will be the derived from the contents of the multiplexing data cells or bits from the input address. The use of control cells in the tag array and control cells and multiplexing data cells in the data array thereby provides for the ability to store and manage information pertaining to at least two different page sizes in a single TLB.

Abstract: A dual port static memory cell with one cycle read-modify-write operation. The static memory cell includes a write line for receiving new data to be written into the static memory cell, switching means for coupling the new data into the static memory cell, and an extended word line generator for generating an extended word line signal. The extended word line signal controls the switching means. During the active state of the extended word line signal, the switching means is enabled to couple new data into the static memory cell while precharge is placed on a bit line coupled to the static memory cell, without disturbing the precharge. The extended word line signal goes active in response to an active state of the word line signal and remains active even after the word line signal goes inactive. The extended word line signal returns to an inactive state prior to the beginning of a new memory cycle. The inactive state of the extended word line signal decouples the new data from the switching means.