Patents by Inventor Eitan Emanuel Rosen

Eitan Emanuel Rosen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuits and methods for selectively latching the output of an adder
    Patent number: 6731138
    Abstract: Methods and circuits for selectively latching the output of an adder are disclosed. One such circuit includes first and second NAND gates, each of which has an input coupled to a clock signal. The outputs of the NAND gates are coupled to a multiplexer. A set dominant latch is coupled to the clock signal and an output of the multiplexer.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: May 4, 2004
    Assignee: Intel Corporatioin
    Inventors: Meiram Heller, Eitan Emanuel Rosen
  • Circuits and methods for selectively latching the output of an adder
    Publication number: 20040021482
    Abstract: Methods and circuits for selectively latching the output of an adder are disclosed. One such circuit includes first and second NAND gates, each of which has an input coupled to a clock signal. The outputs of the NAND gates are coupled to a multiplexer. A set dominant latch is coupled to the clock signal and an output of the multiplexer.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 5, 2004
    Inventors: Meiram Heller, Eitan Emanuel Rosen
  • Counter circuit
    Patent number: 6449327
    Abstract: A system and method are presented for providing a multi-stage counter. In one embodiment, a signal propagates from the most significant bit of the counter to the least significant bit of the counter that indicates that all “more significant” stages of the counter have reached a limit value (e.g., all 1's). Use of this propagating signal means that only the first (or first couple) stages of the counter are time critical, while the remainder are less so. The described counter may have a modular design and may result in lower power consumption.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: September 10, 2002
    Assignee: Intel Corp.
    Inventor: Eitan Emanuel Rosen
  • Counter circuit
    Publication number: 20020085663
    Abstract: A system and method are presented for providing a multi-stage counter. In one embodiment, a signal propagates from the most significant bit of the counter to the least significant bit of the counter that indicates that all “more significant” stages of the counter have reached a limit value (e.g., all 1's). Use of this propagating signal means that only the first (or first couple) stages of the counter are time critical, while the remainder are less so. The described counter may have a modular design and may result in lower power consumption.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventor: Eitan Emanuel Rosen