Patents by Inventor Eitan Fenson

Eitan Fenson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060203838
    Abstract: An EAS tag polling system includes a plurality of EAS tags and a base station, wherein each of the tags transmits an acknowledgement to the base station. The base acknowledgments may be sent passively or actively in response to a request from the base station. The base station discriminates between each acknowledgment received and associates it to the tag from which it had been transmitted. From each acknowledgement received, the base station indicates that a positive response is associated with each of the tags from which the acknowledgement is received and a negative response is associated with each of the tags from which the acknowledgement is not received.
    Type: Application
    Filed: March 8, 2005
    Publication date: September 14, 2006
    Inventors: Richard Howard, Eitan Fenson
  • Patent number: 4958350
    Abstract: A method and apparatus for detection and correction of errors in binary coded information. The method involves receiving a word of binary coded information and grouping the bits of the word of information. Parity bits are generated for each of the groups of bits. The bits are grouped according to three rules: (1) for any three parity bits, there is either one data bit or no data bit whose value effects all three parity bits, (2) for any four parity bits, there is no data bit whose value effects all four, and (3) for any data bit, there are exactly three parity bits whose values are effected by its value. The word bits and parity bits are stored on memory circuits. The bits are stored on the memory circuits in accordance with three rules: (1) no memory circuit may have both data bits and parity bits stored on it, (2) for all bits on a data chip, the sets of parity bits affected by them intersect in one parity bit, (3) for all parity chips, no data bit effects the value of three bits on the chip.
    Type: Grant
    Filed: March 2, 1988
    Date of Patent: September 18, 1990
    Assignee: Stardent Computer, Inc.
    Inventors: Wm. Spencer Worley, III, Eitan Fenson, James R. Weatherford