Abstract: A method and system for soft output multiple-input-multiple-output (MIMO) decoding may include generating a tree-graph based on: MIMO rank, number of bits per layer, and type of modulation, wherein the tree-graph comprises a root node, leaf nodes, nodes, and branches connecting the nodes; performing sphere decoding by determining a radius covering a subset of nodes within said tree-graph; managing, based on the sphere decoding, tables comprising metrics and counter metrics usable for log likelihood ratio (LLR) generation; predicting, based on a specified prediction scheme, counter metrics for paths in the tree-graph that comprise nodes and branches out of the determined radius; and updating the tables comprising the counter metrics with the predicted counter metric, in a case that the predicted counter metrics are better in maximum likelihood terms than the determined counter metrics.

Abstract: A method and system for soft output multiple-input-multiple-output (MIMO) decoding may include generating a tree-graph based on: MIMO rank, number of bits per layer, and type of modulation, wherein the tree-graph comprises a root node, leaf nodes, nodes, and branches connecting the nodes; performing sphere decoding by determining a radius covering a subset of nodes within said tree-graph; managing, based on the sphere decoding, tables comprising metrics and counter metrics usable for log likelihood ratio (LLR) generation; predicting, based on a specified prediction scheme, counter metrics for paths in the tree-graph that comprise nodes and branches out of the determined radius; and updating the tables comprising the counter metrics with the predicted counter metric, in a case that the predicted counter metrics are better in maximum likelihood terms than the determined counter metrics.

Abstract: A system, processor and method are provided for digital signal processing. A processor may initiate processing a sequence of instructions followed by an interrupt. Each instruction may be processed in respective sequential pipeline slots. A branch detector may detect or determine if an instruction is a branch instruction, for example, in turn, for each sequential instruction. In one embodiment, the branch detector may detect if an instruction is a branch instruction until at least a first branch instruction is detected. A processor may annul instructions which are determined to be branch instructions when the interrupt occupies a delay slot associated with the branch instruction. An execution unit may execute at least the sequence of instructions to run a program. The branch detector and/or execution unit may be integral or separate from each other and from the processor.

Abstract: A system, processor and method are provided for digital signal processing A processor may initiate processing a sequence of instructions followed by an interrupt Each instruction may be processed in respective sequential pipeline slots A branch detector may detect or determine if an instruction is a branch instruction, for example, in turn, for each sequential instruction In one embodiment, the branch detector may detect if an instruction is a branch instruction until at least a first branch instruction is detected. A processor may annul instructions which are determined to be branch instructions when the interrupt occupies a delay slot associated with the branch instruction. An execution unit may execute at least the sequence of instructions to run a program.