Abstract: Embodiments include multi-processor systems, including multi-core processor systems, as well as methods for operating the same, in which at least one processor or processor core is configured to receive an instruction directing the at least one processor core to read a value associated with a memory address. In response to receiving the instruction and before execution of the instruction, the at least one processor or processor core causes ones of the plurality of mutually communicatively inter-coupled processor cores to provide a plurality of locally stored values that are stored individually in the respective processor cores and that are associated with the memory address.

Abstract: Some of the embodiments of the present disclosure provide a method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain. Other embodiments are also described and claimed.

Abstract: A method and system are provided for determining a next available address for writing data to a cache memory. In one implementation, a method includes receiving a request for a candidate address in the cache memory, the cache memory divided into a plurality of banks. The method further includes determining a candidate address in each of the cache memory banks using an address determination algorithm, selecting one of the candidate addresses from among the determined candidate addresses using an address selection function different from the address determination algorithm, and returning the selected candidate address in response to the request.

Abstract: Embodiments provide a method comprising receiving, at a cache associated with a central processing unit that is disposed on an integrated circuit, a request to perform a cache operation on the cache; in response to receiving and processing the request, determining that first data cached in a first cache line of the cache is to be written to a memory that is coupled to the integrated circuit; identifying a second cache line in the cache, the second cache line being complimentary to the first cache line; transmitting a single memory instruction from the cache to the memory to write to the memory (i) the first data from the first cache line and (ii) second data from the second cache line; and invalidating the first data in the first cache line, without invalidating the second data in the second cache line.

Abstract: Some of the embodiments of the present disclosure provide a method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain. Other embodiments are also described and claimed.

Abstract: A system includes a first circuit generating error-correction (EC) bits based on test data. Memory comprises a plurality of memory lines each including a data portion storing the test data and an error-correction (EC) portion storing corresponding ones of the EC bits. An input receives the test data. A switching device selectively outputs one of the test data from the input and the EC bits and the test data from the first circuit to the memory. The test data comprise T pairs of test vectors. A first test vector of each of the T pairs of test vectors is an inverse of a second test vector of each of the T pairs of test vectors. Each of the first test vectors in the T pairs of test vectors is unique and each of the second test vectors in the T pairs of test vectors is unique. T is an integer greater than one.

Abstract: A system includes a first circuit that generates error-correction (EC) bits based on received data bits. Memory includes M data portions that store the data bits, where M is an integer greater than one, and M error-correction (EC) portions that store the EC bits. An input receives test data bits. A switching device selectively outputs one of the test data bits from the input and the EC and data bits from the first circuit to one of the M data portions and a corresponding one of the M EC portions. Vector pairs of the test data bits are stored in the memory. Bit values of an nth one of the vector pairs alternate every n bits. Vectors in the vector pairs are shifted n bits relative to each other, where n is an integer greater than zero.

Abstract: A built-in-self-test (BIST) system for testing a memory that includes a scheduler module that generates a first test algorithm based on a set of operational codes. Each operational code defines a test operation to be performed by the first test algorithm on the memory. The BIST system also includes an execution module that applies the first test algorithm to the memory.

Abstract: An integrated circuit, having a method therefor, includes a memory including a plurality of memory lines, each memory line including a plurality of data cells each to store a data bit, and a plurality of error-correction (EC) cells each to store an EC bit corresponding to the data bits stored in the data cells of the memory line; an EC input circuit to generate the EC bits based on the corresponding data bits; an EC output circuit including an EC correction circuit to correct errors in the bits read from the data cells of each of the memory lines in accordance with the bits read from the EC cells of the memory line; and a switch including first inputs to receive the EC bits from the EC input circuit, second inputs to receive test EC bits from EC test nodes of the integrated circuit, and outputs to provide either the EC bits or the EC test bits to the memory in accordance with a test signal.

Abstract: An integrated circuit, having a method therefor, includes a memory including a plurality of memory lines, each memory line including a plurality of data cells each to store a data bit, and a plurality of error-correction (EC) cells each to store an EC bit corresponding to the data bits stored in the data cells of the memory line; an EC input circuit to generate the EC bits based on the corresponding data bits; an EC output circuit including an EC correction circuit to correct errors in the bits read from the data cells of each of the memory lines in accordance with the bits read from the EC cells of the memory line; and a switch including first inputs to receive the EC bits from the EC input circuit, second inputs to receive test EC bits from EC test nodes of the integrated circuit, and outputs to provide either the EC bits or the EC test bits to the memory in accordance with a test signal.