Abstract: A method for estimating an information unit represented by DNA strands, the method includes (a) sequencing the DNA strands to provide noisy copies of an encoded version of the information unit; wherein the information unit comprises information unit elements; (b) neural network (NN) processing the multiple noisy copies by one or more NNs to provide a soft estimate of the encoded information unit; wherein the soft estimate comprises estimated encoded information unit elements and an encoded information unit elements estimated confidence parameter; and (c) decoding the soft estimate of the encoded information unit to provide a prediction of the information unit.

Abstract: There may be provided method for estimating an information unit represented by a cluster of traces that are noisy copies of a synthesized strand, the method may include estimating the information unit by applying processing operations on r-tuples related to the traces, wherein r is smaller than a number (t) of traces of the cluster; wherein processing operations applied on at least some of the r-tuples comprise calculating a length of a shortest common supersequences (SCS) of the r-tuples.

Abstract: A multiple-write enabled flash memory system, comprising: a flash memory comprising at least two planes, wherein each plane comprises multiple blocks, and wherein each block comprises multiple pages; an FTL memory manager configured: to reference one or more clean active blocks on each plane for a first write, wherein the first-write comprises writing one logical page of unmodified data to one physical page, and to reference one or more recycled active block on each plane for a second write, wherein each page of each recycled active block stores data from a previous first-write; and an encoder configured to encode a page of data via a write-once-memory (WOM) code to produce WOM-encoded data, wherein a combination of a target page of each recycled active block is configured to store the WOM-encoded data via a second write.

Abstract: A multiple-write enabled flash memory system, comprising: a flash memory comprising at least two planes, wherein each plane comprises multiple blocks, and wherein each block comprises multiple pages; an FTL memory manager configured: to reference one or more clean active blocks on each plane for a first write, wherein the first-write comprises writing one logical page of unmodified data to one physical page, and to reference one or more recycled active block on each plane for a second write, wherein each page of each recycled active block stores data from a previous first-write; and an encoder configured to encode a page of data via a write-once-memory (WOM) code to produce WOM-encoded data, wherein a combination of a target page of each recycled active block is configured to store the WOM-encoded data via a second write.

Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.

Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.

Abstract: The invention provides a family of 2-write WOM-codes, preferred embodiments of which provide improved WOM-rates. Embodiments of the invention provide constructs for linear codes C having a 2-write WOM-code. Embodiments of the invention provide 2-write WOM-codes that improve the best known WOM-rates known to the present inventors at the time of filing with two writes. Preferred WOM-codes are proved to be capacity achieving when the parity check matrix of the linear code C is chosen uniformly at random. Preferred embodiments of the invention provide an electronic device utilizing an efficient coding scheme of WOM-codes with two write capability. The coding method is based on linear binary codes and allows the electronic device to write information to the memory twice before erasing it. This method can be applied for any kind of memory systems, and in particular for flash memories. The method is shown to outperform all well-known codes.

Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.

Abstract: The invention provides WOM coding methods and electronic devices with error correcting codes that provide single, double and triple error correction. In one coding, if the code corrects two/three errors, it has two/three parts of redundancy bits. For double error correction, if only one part of the redundancy bit has no errors then it is possible to correct one error. For triple error correction, if only one/two parts of the redundancy bits have no errors then it is possible to correct one/two errors. Codes that correct/detect a single, two and three cell-erasures are provided. A code that has three roots, ?1, ?2, ?3, each of which is a primitive element and where every pair of roots generates a double error correcting code, is provided. Codes and coding utilizing a triple error correcting WOM code that can correct an arbitrary number of errors are provided.

Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.

Abstract: Preferred embodiments of the invention provide WOM coding methods and electronic devices with error correcting codes that provide single, double and triple error correction. Preferred codes of the invention also the following property: if the code corrects two/three errors it has two/three parts of redundancy bits. For double error correction, if only one part of the redundancy bit has no errors then it is possible to correct one error. For triple error correction, if only one/two parts of the redundancy bits have no errors then it is possible to correct one/two errors. Preferred methods of the invention use codes that correct/detect a single, two and three cell-erasures. A preferred method of the invention applies a code that has three roots, ah a2, a3, each of which is a primitive element and where every pair of roots generates a double error correcting code.

Abstract: The invention provides a family of 2-write WOM-codes, preferred embodiments of which provide improved WOM-rates. Embodiments of the invention provide constructs for linear codes C having a 2-write WOM-code. Embodiments of the invention provide 2-write WOM-codes that improve the best known WOM-rates known to the present inventors at the time of filing with two writes. Preferred WOM-codes are proved to be capacity achieving when the parity check matrix of the linear code C is chosen uniformly at random. Preferred embodiments of the invention provide an electronic device utilizing an efficient coding scheme of WOM-codes with two write capability. The coding) method is based on linear binary codes and allows the electronic device to write information to the memory twice before erasing it This method can be applied for any kind of memory systems, and in particular for flash memories. The method is shown to outperform all well-known codes.