Abstract: Data processing apparatus, data processing methods, a method and a computer program product are disclosed. The data processing apparatus includes a processor core operable to execute sequences of instructions of a plurality of program threads. The processor core has a plurality of pipeline stages, one of which is an instruction schedule stage having scheduling logic operable, in response to a thread pause instruction within a program thread, to prevent scheduling of instructions from that program thread following the thread pause instruction and instead to schedule instructions from another program thread for execution within the plurality of pipeline stages.

Abstract: Data processing apparatus, data processing methods, a method and a computer program product are disclosed. The data processing apparatus comprises: a processor core operable to execute sequences of instructions of a plurality of program threads, said processor core having a plurality of pipeline stages, one of said pipelined stages being an instruction schedule stage having scheduling logic operable, in response to a thread pause instruction within a program thread, to prevent scheduling of instructions from that program thread following said thread pause instruction and instead to schedule instructions from another program thread for execution within said plurality of pipeline stages In this way, the data processing apparatus does not need to determine whether dependencies exist between instructions or not, but instead can simply continue issuing instructions until a pause instruction is received. This significantly simplifies the operation of the processor core.

Abstract: In a compositing window system, as a respective version of the window for an application is written into a window buffer, a corresponding set of per tile signatures indicative of the content of each respective tile in the window buffer is generated and stored. When an updated version of the window is stored into a window buffer, the set of signature values for the updated version is compared to the set of signature values for the previous version in the window buffer to determine which tiles' content has changed. The set of tiles found to have changed is used to generate a set of regions for a window compositor to write to a window in a display frame buffer to update the window in the display frame buffer to display the new version of the window.

Abstract: A transaction elimination hardware unit controls the writing to a frame buffer in a memory of tiles generated by a tile-based graphics processor. The transaction elimination hardware unit has a signature generator that generates a signature representative of the content of the tile for each tile. A signature comparator then compares the signature of a new tile received from the graphics processor with the signatures of one or more tiles already stored in the frame buffer to see if the signatures match. If the signatures do not match, then the signature comparator controls a write controller to write the new tile to the frame buffer. On the other hand, if the signatures match, then no data is written to the frame buffer and the existing tile is allowed to remain in the frame buffer. In this way, a tile is only written to the frame buffer if it is found by the signature comparison to differ from the tile or tiles that are already stored in the frame buffer that it is compared with.

Abstract: A memory unit and method are disclosed. The memory unit comprises: at least one controller interfaced with at least one corresponding persistent memory device operable to store files in accordance with a file system; and a file mapping unit operable, in response to a virtual file access request from a memory management unit of a processor, the virtual file access request having a virtual address within a virtual address space associated with one of the files identifying data to be accessed, to map the virtual address to a physical address of the data within the one of the files using pre-stored mapping information and to issue a physical access request having the physical address to access the data within the one of the files.

Abstract: A data processing apparatus, a data processing method and a computer program product are disclosed. In an embodiment, the data processing apparatus comprises: a processor comprising a plurality of parallel lanes for parallel processing of sets of threads, each lane comprising a plurality of pipelined stages, the pipelined stages of each lane being operable to process instructions from the sets of threads; and scheduling logic operable to schedule instructions for processing by the lanes, the scheduling logic being operable to identify that one of the sets of threads being processed is to be split into a plurality of sub-sets of threads and to schedule at least two of the plurality of sub-sets of threads for processing by different pipelined stages concurrently.

Abstract: A graphics processor 1 includes after its tile rendering logic 40, a transaction elimination unit 5 that includes data block generation logic 41 and block comparison logic 43. The block generation logic 41 generates data blocks from the rendered tiles produced by the tile rendering logic 40. The data blocks are then stored in buffers 42. Comparison logic 43 then compares a new data block with the previous data block (which will already be stored in the buffers 42), and generates an output metadata bit indicating whether the blocks can be considered to be the same or not, on the basis of the comparison. The meta-data output bits are stored appropriately in a meta-data bitmap 45 in main memory 2 that is associated with the output data array in question. If the blocks are determined to be different by the comparison logic then the new data block is written from the buffers 42 to the frame buffer 44 in the main memory 2.

Abstract: A memory unit and method are disclosed. The memory unit comprises: at least one controller interfaced with at least one corresponding persistent memory device operable to store files in accordance with a file system; and a file mapping unit operable, in response to a virtual file access request from a memory management unit of a processor, the virtual file access request having a virtual address within a virtual address space associated with one of the files identifying data to be accessed, to map the virtual address to a physical address of the data within the one of the files using pre-stored mapping information and to issue a physical access request having the physical address to access the data within the one of the files.

Abstract: A data processing apparatus, a data processing method and a computer program product are disclosed. In an embodiment, the data processing apparatus comprises: a processor comprising a plurality of parallel lanes for parallel processing of sets of threads, each lane comprising a plurality of pipelined stages, the pipelined stages of each lane being operable to process instructions from the sets of threads; and scheduling logic operable to schedule instructions for processing by the lanes, the scheduling logic being operable to identify that one of the sets of threads being processed is to be split into a plurality of sub-sets of threads and to schedule at least two of the plurality of sub-sets of threads for processing by different pipelined stages concurrently.

Abstract: A data compressor has a delta value calculator which receives data items and determines if a related data item to a received data item is stored in a data store. If the related item is stored, the delta value calculator retrieves the related data item from the data store and calculates a delta value from the received data item and the related data item. If the related item is not stored, then the delta value is calculated from the received data item and a predetermined value. A data store controller accesses the data store in response to receipt of a data item and determines if a storage location is allocated to the data item. If there is an allocated storage location for the data item, the data item is stored in the allocated storage location; and if not then a storage location is allocated to the data item.

Abstract: In a compositing window system, as a respective version of the window for an application is written into a window buffer, a corresponding set of per tile signatures indicative of the content of each respective tile in the window buffer is generated and stored. When an updated version of the window is stored into a window buffer, the set of signature values for the updated version is compared to the set of signature values for the previous version in the window buffer to determine which tiles' content has changed. The set of tiles found to have changed is used to generate a set of regions for a window compositor to write to a window in a display frame buffer to update the window in the display frame buffer to display the new version of the window.

Abstract: A graphics processing apparatus 2 includes graphics processing pipelines 8. The graphics processing pipelines 8 include a programmable hardware stage 12, a pipeline memory 22 and writeback circuitry 16. Programmable resolving circuitry 18 is provided by the programmable hardware stage 12 within each pipeline and is responsive to one or more graphics program instructions to read pixel values at a first resolution generated within the pipeline memory 22 by pixel value generating circuitry 18 provided by the programmable hardware stage 12 and to perform a resolving operation upon these pixels values so as to generate pixel values at a second resolution. These pixel values at the second resolution are then written back to a frame buffer memory 6.

Abstract: A graphics processor 1 includes after its tile rendering logic 40, a transaction elimination unit 5 that includes data block generation logic 41 and block comparison logic 43. The block generation logic 41 generates data blocks from the rendered tiles produced by the tile rendering logic 40. The data blocks are then stored in buffers 42. Comparison logic 43 then compares a new data block with the previous data block (which will already be stored in the buffers 42), and generates an output metadata bit indicating whether the blocks can be considered to be the same or not, on the basis of the comparison. The meta-data output bits are stored appropriately in a meta-data bitmap 45 in main memory 2 that is associated with the output data array in question. If the blocks are determined to be different by the comparison logic then the new data block is written from the buffers 42 to the frame buffer 44 in the main memory 2.

Abstract: A transaction elimination hardware unit 5 controls the writing to a frame buffer in a memory 2 of tiles generated by a tile-based graphics processor. The transaction elimination hardware unit 5 has a signature generator 20 that generates a signature representative of the content of the tile for each tile. A signature comparator 23 then compares the signature of a new tile received from the graphics processor with the signatures of one or more tiles already stored in the frame buffer to see if the signatures match. If the signatures do not match, then the signature comparator 23 controls a write controller 24 to write the new tile to the frame buffer. On the other hand, if the signatures match, then no data is written to the frame buffer and the existing tile is allowed to remain in the frame buffer. In this way, a tile is only written to the frame buffer if it is found by the signature comparison to differ from the tile or tiles that are already stored in the frame buffer that it is compared with.

Abstract: A filled shape is defined by edge data forming one or more boundaries thereof. Local shape data is generated from the edge data for each graphics region overlapped by the filled shape. The local shape data separately represents for each graphic region at least any edge of the filled shape within the graphics region and an overlap value indicative of a difference between a number of times the boundaries of the filled shape surround the region in a clockwise direction and the number of times the boundaries surround the region in a counter-clockwise direction. For each graphics region having local shape data, the local shape data is used to generate pixel values for pixels within that graphics region that are within the filled shape to be drawn.

Abstract: A graphics processing apparatus 2 includes graphics processing pipelines 8. The graphics processing pipelines 8 include a programmable hardware stage 12, a pipeline memory 22 and writeback circuitry 16. Programmable resolving circuitry 18 is provided by the programmable hardware stage 12 within each pipeline and is responsive to one or more graphics program instructions to read pixel values at a first resolution generated within the pipeline memory 22 by pixel value generating circuitry 18 provided by the programmable hardware stage 12 and to perform a resolving operation upon these pixels values so as to generate pixel values at a second resolution. These pixel values at the second resolution are then written back to a frame buffer memory 6.