Patents by Inventor EJ Wu

EJ Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for integrally checking chip and package substrate layouts for errors
    Patent number: 7257784
    Abstract: A method and system for integrally checking a chip layout dataset and a package substrate layout dataset for errors are disclosed. The package substrate layout dataset is converted from a first format into a second format in which the chip layout dataset is provided. The chip layout dataset of the second format is combined with the package substrate layout dataset of the second format into a combined dataset. The combined dataset is then checked for errors or design rule violations.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: August 14, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Lin Cheng, EJ Wu, Shih-Cheng Chang, Kuo-Yin Chen