Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: In one embodiment, a system for deskewing signals on parallel bus channels includes several parallel channels that carry several data input signals and a pair of complementary voltage and timing reference (VTR) signals. The system also includes several receivers, with each receiver coupled to receive a data input signal and the pair of complementary VTR signals. The output of each receiver is based in part on a comparison of the received data input signal with the pair of complementary VTR signals. In one embodiment, a pair of VTR signals is selected from several pairs of VTR signals to widen the skew band on each channel. In one embodiment, each channel is skewed using a programmable delay circuit having a delay value based on the alignment of a data input signal relative to a pair of complementary VTR signals.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and/SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and/SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against/SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and/SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and/SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using XOR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is decoupled if no transition occurs.

Abstract: In one embodiment, a system for deskewing signals on parallel bus channels includes several parallel channels that carry several data input signals and a pair of complementary voltage and timing reference (VTR) signals. The system also includes several receivers, with each receiver coupled to receive a data input signal and the pair of complementary VTR signals. The output of each receiver is based in part on a comparison of the received data input signal with the pair of complementary VTR signals. In one embodiment, a pair of VTR signals is selected from several pairs of VTR signals to widen the skew band on each channel. In one embodiment, each channel is skewed using a programmable delay circuit having a delay value based on the alignment of a data input signal relative to a pair of complementary VTR signals.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using XOR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is decoupled if no transition occurs.

Abstract: A system enables the capture of incoming signals from different components when the skew between the different components is higher than the signal rate. The system comprises a first port for serially receiving a first signal at a signal rate from a first component; a second port for serially receiving a second signal at the signal rate from a second component; a first serial-to-parallel conversion circuit for performing serial-to-n-bit-parallel conversion of the first signal, n being greater than one; and a second serial-to-parallel conversion circuit for performing serial-to-n-bit parallel conversion of the second signal.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and/SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and/SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against/SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and/SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and/SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using XOR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Abstract: A semiconductor memory device such as a DRAM has an internal oscillator to provide a periodic clock signal. During a read operation, output data is generated synchronized to the internal clock signal, and an external control signal is provided also synchronized to the internal clock signal. A requesting device utilizes the external control signal for fetching data from the memory device at high speed with improved setup and hold time. The control signal output is active only during a read operation, thereby reducing power consumption. Additionally, a common line is used for receiving address, instructions, and data. This drastically reduces the number of pins for interfacing to a memory device.

Abstract: The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device capable of executing a self-refresh operation to achieve a low power consumption, and of executing a burn-in operation in wafer and package states as well. A semiconductor memory device comprising a plurality of memory cells arranged in rows and columns, a word line being arranged in each row to select the rows of the plurality of memory cells in response to an input of row address, a bit line being arranged in each column to select the columns of the plurality of memory cells in response to an input of column address, and the row address for designating a row accessed in a previous selection operation upon selection of an arbitrary word line comprising a controller for executing the arbitrary word line selection.

Abstract: The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device capable of executing a self-refresh operation to achieve a low power consumption, and of executing a burn-in operation in wafer and package states as well. A semiconductor memory device comprising a plurality of memory cells arranged in rows and columns, a word line being arranged in each row to select the rows of the plurality of memory cells in response to an input of row address, a bit line being arranged in each column to select the columns of the plurality of memory cells in response to an input of column address, and the row address for designating a row accessed in a previous selection operation upon selection of an arbitrary word line comprising a controller for executing the arbitrary word line selection.

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Abstract: An SRAM uses PMOS column pass gates in conjunction with PMOS column loads which can be selectively deactivated during write operations. Address decoding for the pass gates and loads can be done outside of the memory array to maximize device density. This arrangement provides densities comparable to those achievable with NMOS column pass gates, but without the read access time penalties associated therewith.