Abstract: A flexible architecture component for providing data integration and exchange between a plurality of client applications is disclosed. The client applications are coupled to a network and access respective data sources, wherein the data sources of each of the client applications may be stored in different formats and are not directly accessible by the other client applications. Aspects of the present invention include providing an adapter API that provides a first set of methods for the client applications to use to translate data into XML. Each of the client applications is then modified to invoke the methods in the adapter API to convert data in their respective data sources into XML format and to have the XML formatted data imported into a database on a server, thereby standardizing the data from the data sources.

Abstract: A method, system, and program product includes an interactive network-based site that permits a user to specify, compile, analyze and export memory configuration data associated with at least one memory component manufactured in a manufacturing environment. Such memory configuration data can be specified, compiled analyzed or exported in response to a particular user input through the interactive network-based site.

Abstract: A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.

Abstract: A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.

Abstract: A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state output bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state output bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals. The memory produces an output signal dependent upon the enable signal generation logic output, and thus upon a logic level of the tri-state output bit line.

Abstract: A method, system, and program product includes an interactive network-based site that permits a user to specify, compile, analyze and export memory configuration data associated with at least one memory component manufactured in a manufacturing environment. Such memory configuration data can be specified, compiled analyzed or exported in response to a particular user input through the interactive network-based site.

Abstract: A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock signal for testing the latch based random access memory wherein the scan clock signal has a first scan clock period for a shift cycle and a second scan clock period for a capture cycle.

Abstract: A latch based random access memory includes an input data register; an input data buffer coupled to the input data register; a latch array coupled to the input data buffer; and a latch array bypass multiplexer for selecting one of the input data buffer and the latch array in response to a memory scan mode signal to generate a first data output of the latch based random access memory from the input data buffer during logic scan testing and a second data output of the latch based random access memory from the latch array during memory scan testing.

Abstract: A method for notification of a first new cell is disclosed. The method generally includes the steps of (A) generating a first report for a circuit design comprising a plurality of first cells including the first new cell by executing a rule check on the circuit design, (B) comparing the first report with a database comprising a plurality of second cells already manufactured and (C) notifying a client of the first new cell in response to the first new cell not matching any of the second cells.

Abstract: A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock signal for testing the latch based random access memory wherein the scan clock signal has a first scan clock period for a shift cycle and a second scan clock period for a capture cycle.

Abstract: A method and system for dynamically generating database queries is disclosed. The method and system include storing web interface data, including query attributes for a database, in one more tables. The attributes are then retrieved from the tables and displayed in a graphical user interface web page for user selection. Based on the attributes selected by the user, a SQL query is dynamically generated. The method and system further include displaying results of the SQL query to the user in graphical format, thereby enabling dynamic generation of custom queries.

Abstract: A method for notification of a first new cell is disclosed. The method generally includes the steps of (A) generating a first report for a circuit design comprising a plurality of first cells including the first new cell by executing a rule check on the circuit design, (B) comparing the first report with a database comprising a plurality of second cells already manufactured and (C) notifying a client of the first new cell in response to the first new cell not matching any of the second cells.

Abstract: A latch based random access memory includes an input data register; an input data buffer coupled to the input data register; a latch array coupled to the input data buffer; and a latch array bypass multiplexer for selecting one of the input data buffer and the latch array in response to a memory scan mode signal to generate a first data output of the latch based random access memory from the input data buffer during logic scan testing and a second data output of the latch based random access memory from the latch array during memory scan testing.

Abstract: A flexible architecture component for providing data integration and exchange between a plurality of client applications is disclosed. The client applications are coupled to a network and access respective data sources, wherein the data sources of each of the client applications may be stored in different formats and are not directly accessible by the other client applications. Aspects of the present invention include providing an adapter API that provides a first set of methods for the client applications to use to translate data into XML. Each of the client applications is then modified to invoke the methods in the adapter API to convert data in their respective data sources into XML format and to have the XML formatted data imported into a database on a server, thereby standardizing the data from the data sources.