Patents by Inventor Ekanayake Ajith Amerasekera

Ekanayake Ajith Amerasekera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PMOS electrostatic discharge (ESD) protection device
    Patent number: 7196887
    Abstract: A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A snapback leg in curves capable of being produced in accordance with one or more aspects of the present invention is removed, and a trigger voltage at which the device turns on is thereby reduced so as to be less than a second voltage corresponding to a second breakdown region.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Gianluca Boselli, Vijay Kumar Reddy, Ekanayake Ajith Amerasekera
  • PMOS electrostatic discharge (ESD) protection device
    Publication number: 20040240128
    Abstract: A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A snapback leg in curves capable of being produced in accordance with one or more aspects of the present invention is removed, and a trigger voltage at which the device turns on is thereby reduced so as to be less than a second voltage corresponding to a second breakdown region.
    Type: Application
    Filed: May 28, 2003
    Publication date: December 2, 2004
    Inventors: Gianluca Boselli, Vijay Kumar Reddy, Ekanayake Ajith Amerasekera
  • ESD protection circuit for dual 3V/5V supply devices using single thickness gate oxides
    Patent number: 6078083
    Abstract: An ESD protection circuit for dual 3V/5V supply devices. ESD protection circuit 10 comprises a switching element 12 connected between a bond pad 14 and primary protection device 16. Primary protection device 16 comprises MOS circuitry designed for 3V operation that suffers from oxide reliability problems when 5V signals are applied directly. Switching element 12 separates the primary protection device 16 from 5V signals which may appear at bond pad 14.
    Type: Grant
    Filed: August 16, 1995
    Date of Patent: June 20, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Ekanayake Ajith Amerasekera, Charvaka Duvvury
  • Gate coupled SCR for ESD protection circuits
    Patent number: 5907462
    Abstract: A protection device comprising a gate-coupled silicon-controlled rectifier (SCR) (100), SCR (100) comprises an anode (105) formed in n-well (104) and connected to a pad (128) and a cathode (111) connected to ground. A gate-coupled NMOS transistor (120) has a gate (116) connected through a resistive element (118) to ground. A n+ region (112) forms both the cathode (111) and a source of the NMOS transistor (120). N-well (104) forms the drain. Stress voltage is coupled from pad (128) to gate electrode (116) causing NMOS transistor (120) to conduct. This, in turn, triggers SCR (100) which dissipates the stress current at the pad (128). The coupled voltage at gate electrode (116) dissipates within a designed time constant through resistive element (118).
    Type: Grant
    Filed: September 7, 1994
    Date of Patent: May 25, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Charvaka Duvvury, Ping Yang, Ekanayake Ajith Amerasekera