Patents by Inventor Ekaterina M. Ambroladze
Ekaterina M. Ambroladze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240119000Abstract: A data processing system includes a system fabric coupling a coherence manager and an input/output (I/O) requestor. The I/O requestor issues a first snoop request of a first I/O store operation and a subsequent second snoop request of a second I/O store operation. Each of the first and second snoop requests specifies an update to a respective storage location identified by a coherent memory address. The I/O requestor receives respective ownership coherence responses for each of the first and second I/O store operations. The respective first and second ownership coherence responses indicate the coherence manager has concurrent coherence ownership of the memory address for both the first and second I/O store operations. In response to receipt of each of the ownership coherence responses, the I/O requestor issues respective first and second execute coherence responses to command the coherence manager to initiate updates to the respective storage locations.Type: ApplicationFiled: October 10, 2022Publication date: April 11, 2024Inventors: Ekaterina M. Ambroladze, Matthias Klein, Sascha Junghans, Kevin Lopes
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Publication number: 20240061803Abstract: Serialized broadcast command messaging in a distributed symmetric multiprocessing (SMP) system, including: sending a serial broadcast command from a home chip to a plurality of other chips comprising serial primary chip, wherein each chip of the plurality of other chips comprises a broadcast controller mapped to a home chip broadcast controller; assigning, by the serial primary chip, a tag to the serial broadcast command; sending, from the serial primary chip, to the home chip and a remainder of the plurality of other chips, the tag; and broadcasting, by the home chip and each chip of the plurality of other chips, the serial broadcast command in an order based on the tag of the serial broadcast command.Type: ApplicationFiled: August 16, 2022Publication date: February 22, 2024Inventors: HAILEY NICHOLSON, ROBERT J. SONNELITTER, III, EKATERINA M. AMBROLADZE, DEANNA POSTLES DUNN BERGER, VESSELINA PAPAZOVA, GARY E. STRAIT, CRAIG R. WALTERS
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Publication number: 20230315644Abstract: Castout handling in a distributed cache topology, including: detecting, by a first cache of a plurality of caches, a cache miss; providing, by the first cache to each other cache of the plurality of caches, a message comprising: data indicating a cache address corresponding to the cache miss; and data indicating a cache line to be evicted.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: ROBERT J. SONNELITTER, III, EKATERINA M. AMBROLADZE, TIMOTHY BRONSON, MICHAEL A. BLAKE, TU-AN T. NGUYEN
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Patent number: 11042483Abstract: A computer system includes a cache and processor. The cache includes a plurality of data compartments configured to store data. The data compartments are arranged as a plurality of data rows and a plurality of data columns. Each data row is defined by an addressable index. The processor is in signal communication with the cache, and is configured to operate in a full cache purge mode and a selective cache purge mode. In response to invoking one or both of the full cache purge mode and the selective cache purge mode, the processor performs a pipe pass on a selected addressable index to determine a number of valid compartments and a number of invalid compartments, and performs an eviction operation on the valid compartments while skipping the eviction operation on the invalid compartments.Type: GrantFiled: April 26, 2019Date of Patent: June 22, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Deanna P. D. Berger, Vesselina Papazova
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Patent number: 10915461Abstract: Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.Type: GrantFiled: March 5, 2019Date of Patent: February 9, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Matthias Klein, Craig Walters, Kevin Lopes, Michael A. Blake, Tim Bronson, Kenneth Klapproth, Vesselina Papazova, Hieu T Huynh
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Patent number: 10901902Abstract: Methods and systems for cache management are provided. Aspects include providing a drawer including a plurality of clusters, each of the plurality of clusters including a plurality of processor each having one or more cores, wherein each of the one or more cores shares a first cache memory, providing a second cache memory shared among the plurality of clusters, and receiving a cache line request from one of the one or more cores to the first cache memory, wherein the first cache memory sends a request to a memory controller to retrieve the cache line from a memory, store the cache line in the first cache memory, create a directory state associated with the cache line, and provide the directory state to the second cache memory to create a directory entry for the cache line.Type: GrantFiled: March 21, 2019Date of Patent: January 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad G. Wilson, Robert J Sonnelitter, III, Tim Bronson, Ekaterina M. Ambroladze, Hieu T Huynh, Jason D Kohl, Chakrapani Rayadurgam
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Patent number: 10831661Abstract: Processing simultaneous data requests regardless of active request in the same addressable index of a cache. In response to the cache miss in the given congruence, if the number of other compartments in the given congruence class that have an active operation is less than a predetermined threshold, setting a Do Not Cast Out (DNCO) pending indication for each of the compartments that have an active operation in order to block access to each of the other compartments that have active operations and, if the number of other compartments in the given congruence class that have an active operation is not less than a predetermined threshold, blocking another cache miss from occurring in the compartments of the given congruence class by setting a congruence class block pending indication for the given congruence class in order to block access to each of the other compartments of the given congruence class.Type: GrantFiled: April 10, 2019Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekaterina M. Ambroladze, Tim Bronson, Robert J. Sonnelitter, III, Deanna P. D. Berger, Chad G. Wilson, Kenneth Douglas Klapproth, Arthur O'Neill, Michael A. Blake, Guy G. Tracy
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Patent number: 10824565Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.Type: GrantFiled: March 11, 2019Date of Patent: November 3, 2020Assignee: International Business Machines CorporationInventors: Ekaterina M Ambroladze, Deanna P Berger, Michael F Fee, Arthur J O'Neill, Robert J Sonnelitter, III
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Publication number: 20200341902Abstract: A computer system includes a cache and processor. The cache includes a plurality of data compartments configured to store data. The data compartments are arranged as a plurality of data rows and a plurality of data columns. Each data row is defined by an addressable index. The processor is in signal communication with the cache, and is configured to operate in a full cache purge mode and a selective cache purge mode. In response to invoking one or both of the full cache purge mode and the selective cache purge mode, the processor performs a pipe pass on a selected addressable index to determine a number of valid compartments and a number of invalid compartments, and performs an eviction operation on the valid compartments while skipping the eviction operation on the invalid compartments.Type: ApplicationFiled: April 26, 2019Publication date: October 29, 2020Inventors: Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Deanna P. D. Berger, Vesselina Papazova
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Publication number: 20200327058Abstract: Processing simultaneous data requests regardless of active request in the same addressable index of a cache. In response to the cache miss in the given congruence, if the number of other compartments in the given congruence class that have an active operation is less than a predetermined threshold, setting a Do Not Cast Out (DNCO) pending indication for each of the compartments that have an active operation in order to block access to each of the other compartments that have active operations and, if the number of other compartments in the given congruence class that have an active operation is not less than a predetermined threshold, blocking another cache miss from occurring in the compartments of the given congruence class by setting a congruence class block pending indication for the given congruence class in order to block access to each of the other compartments of the given congruence class.Type: ApplicationFiled: April 10, 2019Publication date: October 15, 2020Inventors: Ekaterina M. Ambroladze, Tim Bronson, Robert J. Sonnelitter, III, Deanna P. D. Berger, Chad G. Wilson, Kenneth Douglas Klapproth, Arthur O'Neill, Michael A. Blake, Guy G. Tracy
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Publication number: 20200301831Abstract: Methods and systems for cache management are provided. Aspects include providing a drawer including a plurality of clusters, each of the plurality of clusters including a plurality of processor each having one or more cores, wherein each of the one or more cores shares a first cache memory, providing a second cache memory shared among the plurality of clusters, and receiving a cache line request from one of the one or more cores to the first cache memory, wherein the first cache memory sends a request to a memory controller to retrieve the cache line from a memory, store the cache line in the first cache memory, create a directory state associated with the cache line, and provide the directory state to the second cache memory to create a directory entry for the cache line.Type: ApplicationFiled: March 21, 2019Publication date: September 24, 2020Inventors: Chad G. Wilson, Robert J Sonnelitter, III, Tim Bronson, Ekaterina M. Ambroladze, Hieu T Huynh, Jason D Kohl, Chakrapani Rayadurgam
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Publication number: 20200285592Abstract: Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.Type: ApplicationFiled: March 5, 2019Publication date: September 10, 2020Inventors: Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Matthias Klein, Craig Walters, Kevin Lopes, Michael A. Blake, Tim Bronson, Kenneth Klapproth, Vesselina Papazova, Hieu T Huynh
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Patent number: 10649908Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.Type: GrantFiled: February 21, 2019Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Deanna P. D. Berger, Michael A. Blake, Pak-kin Mak, Robert J. Sonnelitter, III, Guy G. Tracy, Chad G. Wilson
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Patent number: 10528253Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.Type: GrantFiled: November 5, 2014Date of Patent: January 7, 2020Assignee: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Garrett M. Drapala, Norbert Hagspiel, Sascha Junghans, Matthias Klein, Gary E. Strait
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Patent number: 10529396Abstract: A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.Type: GrantFiled: June 22, 2017Date of Patent: January 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekaterina M. Ambroladze, Sascha Junghans, Matthias Klein, Pak-Kin Mak, Robert J. Sonnelitter, III, Chad G. Wilson
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Patent number: 10437729Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.Type: GrantFiled: April 19, 2017Date of Patent: October 8, 2019Assignee: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Deanna P. D. Berger, Michael A. Blake, Pak-kin Mak, Robert J. Sonnelitter, III, Guy G. Tracy, Chad G. Wilson
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Patent number: 10402328Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.Type: GrantFiled: January 2, 2018Date of Patent: September 3, 2019Assignee: International Business Machines CorporationInventors: Ekaterina M Ambroladze, Deanna P Berger, Michael F Fee, Arthur J O'Neill, Robert J Sonnelitter, III
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Patent number: 10394712Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.Type: GrantFiled: January 2, 2018Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Ekaterina M Ambroladze, Deanna P Berger, Michael F Fee, Arthur J O'Neill, Robert J Sonnelitter, III
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Publication number: 20190251036Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.Type: ApplicationFiled: May 3, 2019Publication date: August 15, 2019Inventors: Ekaterina M. Ambroladze, Deanna P. D. Berger, Michael A. Blake, Pak-kin Mak, Robert J. Sonnelitter, III, Guy G. Tracy, Chad G. Wilson
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Publication number: 20190251037Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.Type: ApplicationFiled: May 3, 2019Publication date: August 15, 2019Inventors: Ekaterina M. Ambroladze, Deanna P. D. Berger, Michael A. Blake, Pak-kin Mak, Robert J. Sonnelitter, III, Guy G. Tracy, Chad G. Wilson