Abstract: An apparatus may include detection circuitry configured to detect a presence of a host clock signal on a host clock line, and detect a level of a host supply voltage upon detection of the host clock signal. The detection circuitry may configure a core regulator in a regulation mode or in a bypass mode based on the detected level of the host supply voltage. Additionally, components of analog circuitry of a non-volatile memory system may be partitioned into different supply voltage domains, with those components active during a sleep state receiving one supply voltage and those components inactive during the sleep state receiving a different supply voltage.

Abstract: An apparatus may include detection circuitry configured to detect a presence of a host clock signal on a host clock line, and detect a level of a host supply voltage upon detection of the host clock signal. The detection circuitry may configure a core regulator in a regulation mode or in a bypass mode based on the detected level of the host supply voltage. Additionally, components of analog circuitry of a non-volatile memory system may be partitioned into different supply voltage domains, with those components active during a sleep state receiving one supply voltage and those components inactive during the sleep state receiving a different supply voltage.

Abstract: A data storage device includes a non-volatile memory and a host interface. A method includes supplying a first supply voltage to the host interface during a first mode of operation of the non-volatile memory. The method further includes supplying a second supply voltage to the host interface in response to a transition from the first mode of operation to a second mode of operation of the non-volatile memory.

Abstract: A data storage device includes a signal source. A load is responsive to the signal source. A method includes adjusting an impedance of the load to reduce an impedance mismatch between the signal source and the load.

Abstract: A data storage device includes a memory and a controller. A method includes calibrating a first portion of the interface in response to a first bit transition from a first bit value to a second bit value of data to be sent via the interface.

Abstract: A data storage device includes an interface. A method includes charging a voltage at a node of the interface using a first supply voltage. The method further includes partially discharging the voltage to a voltage supply node of the data storage device. The voltage supply node is associated with a second supply voltage.

Abstract: A data storage device includes a signal source. A load is responsive to the signal source. A method includes adjusting an impedance of the load to reduce an impedance mismatch between the signal source and the load.

Abstract: A data storage device includes a memory and a controller. A method includes calibrating a first portion of the interface in response to a first bit transition from a first bit value to a second bit value of data to be sent via the interface.

Abstract: A data storage device includes a non-volatile memory and a host interface. A method includes supplying a first supply voltage to the host interface during a first mode of operation of the non-volatile memory. The method further includes supplying a second supply voltage to the host interface in response to a transition from the first mode of operation to a second mode of operation of the non-volatile memory.

Abstract: In an embodiment, a circuit is disclosed that includes a current mirror including a first transistor pair and a second transistor pair. The first transistor pair includes a first transistor and a second transistor. The second transistor pair includes cascode transistors. The circuit also includes an operational amplifier having an output coupled to both the first transistor and the second transistor.

Abstract: A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Abstract: A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Abstract: An electronic product includes an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product. The capless regulator module includes both a low-power sub-module and a high-power sub-module. Control logic of the ASIC is configured to determine if an external capacitance is present. If so, the control logic causes the high-power capless regulator sub-module to be used during a power-up phase of the ASIC; if not, only the low-power capless regulator sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Abstract: In an embodiment, a circuit is disclosed that includes a current mirror including a first transistor pair and a second transistor pair. The first transistor pair includes a first transistor and a second transistor. The second transistor pair includes cascode transistors. The circuit also includes an operational amplifier having an output coupled to both the first transistor and the second transistor.