Patents by Inventor El Mehdi Bazizi
El Mehdi Bazizi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929433Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.Type: GrantFiled: November 10, 2021Date of Patent: March 12, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Ignasi Cortes, Alban Zaka, Tom Herrmann, El Mehdi Bazizi, Richard Francis Taylor, III
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Publication number: 20240069448Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Inventors: Prayudi LIANTO, Liu JIANG, Marvin Louis BERNT, El Mehdi BAZIZI, Guan Huei SEE
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Patent number: 11899376Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.Type: GrantFiled: August 31, 2022Date of Patent: February 13, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Prayudi Lianto, Liu Jiang, Marvin Louis Bernt, El Mehdi Bazizi, Guan Huei See
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Publication number: 20240014214Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by a dry oxidation process resulting rearrangement of the cladding material and first material.Type: ApplicationFiled: July 10, 2023Publication date: January 11, 2024Applicant: Applied Materials, Inc.Inventors: Sai Hooi Yeong, Jody A. Fronheiser, Benjamin Colombeau, Balasubramanian Pranatharthiharan, El Mehdi Bazizi, Ashish Pal
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Publication number: 20230299199Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.Type: ApplicationFiled: May 26, 2023Publication date: September 21, 2023Applicant: Applied Materials, Inc.Inventors: Ashish Pal, Mehdi Saremi, El Mehdi Bazizi, Benjamin Colombeau
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Publication number: 20230260908Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming distinct and separate bottom dielectric isolation layers underneath the source/drain and underneath the gate of a gate all around device. Selectively remove of the bottom dielectric isolation layer underneath the source/drain results in better backside power rail (BPR) via alignment to the source/drain epi and reduces reliability and gate-shorting problems.Type: ApplicationFiled: February 7, 2023Publication date: August 17, 2023Applicant: Applied Materials, Inc.Inventors: Andrew Yeoh, Benjamin Colombeau, Balasubramanian Pranatharthiharan, Ashish Pal, El Mehdi Bazizi
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Publication number: 20230260909Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a diffusion break opening on the backside and filling with a diffusion break material to serve as a planarization stop. In some embodiments, a single diffusion break opening is formed. In other embodiments, a mixed diffusion break opening is formed.Type: ApplicationFiled: February 7, 2023Publication date: August 17, 2023Applicant: Applied Materials, Inc.Inventors: Andrew Yeoh, Benjamin Colombeau, Balasubramanian Pranatharthiharan, El Mehdi Bazizi, Ashish Pal
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Patent number: 11705490Abstract: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 ?m. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.Type: GrantFiled: February 8, 2021Date of Patent: July 18, 2023Assignee: Applied Materials, Inc.Inventors: Ashish Pal, El Mehdi Bazizi, Siddarth Krishnan, Xing Chen, Lan Yu, Tyler Sherwood
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Patent number: 11699755Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.Type: GrantFiled: August 24, 2020Date of Patent: July 11, 2023Assignee: Applied Materials, Inc.Inventors: Ashish Pal, Mehdi Saremi, El Mehdi Bazizi, Benjamin Colombeau
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Publication number: 20230170400Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a source/drain cavity and filling the cavity with a sacrificial layer. The sacrificial layer is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.Type: ApplicationFiled: November 28, 2022Publication date: June 1, 2023Applicant: Applied Materials, Inc.Inventors: Ashish Pal, Benjamin Colombeau, El Mehdi Bazizi, Balasubramanian Pranatharthiharan
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Publication number: 20230067331Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is etched and then crystallized. Epitaxially growth of the source and drain regions then proceeds, with growth advantageously occurring on the bottom and sidewalls of the source and drain regions.Type: ApplicationFiled: August 26, 2022Publication date: March 2, 2023Applicant: Applied Materials, Inc.Inventors: Ashish Pal, El Mehdi Bazizi, Benjamin Colombeau
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Publication number: 20230064183Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.Type: ApplicationFiled: August 29, 2022Publication date: March 2, 2023Applicant: Applied Materials, Inc.Inventors: Suketu Arun Parikh, Ashish Pal, El Mehdi Bazizi, Andrew Yeoh, Nitin K. Ingle, Arvind Sundarrajan, Guan Huei See, Martinus Maria Berkens, Sameer A. Deshpande, Balasubramanian Pranatharthiharan, Yen-Chu Yang
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Publication number: 20230061392Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.Type: ApplicationFiled: August 29, 2022Publication date: March 2, 2023Applicant: Applied Materials, Inc.Inventors: Suketu Arun Parikh, Ashish Pal, El Mehdi Bazizi, Andrew Yeoh, Nitin K. Ingle, Arvind Sundarrajan, Guan Huei See, Martinus Maria Berkens, Sameer A. Deshpande, Balasubramanian Pranatharthiharan, Yen-Chu Yang
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Publication number: 20230068312Abstract: Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.Type: ApplicationFiled: August 29, 2022Publication date: March 2, 2023Applicant: Applied Materials, Inc.Inventors: Suketu Arun Parikh, Ashish Pal, El Mehdi Bazizi, Andrew Yeoh, Nitin K. Ingle, Arvind Sundarrajan, Guan Huei See, Martinus Maria Berkens, Sameer A. Deshpande, Balasubramanian Pranatharthiharan, Yen-Chu Yang
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Publication number: 20230008858Abstract: Embodiments of processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: depositing, via a first epitaxial growth process, an n-doped silicon material onto a substrate to form an n-doped layer while adjusting a ratio of dopant precursor to silicon precursor so that a dopant concentration of the n-doped layer increases from a bottom of the n-doped layer to a top of the n-doped layer; etching the n-doped layer to form a plurality of trenches having sidewalls that are tapered and a plurality of n-doped pillars therebetween; and filling the plurality of trenches with a p-doped material via a second epitaxial growth process to form a plurality of p-doped pillars.Type: ApplicationFiled: July 8, 2021Publication date: January 12, 2023Inventors: Ashish PAL, Yi ZHENG, El Mehdi BAZIZI
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Publication number: 20220359289Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: Micromaterials LLCInventors: Regina Freed, Madhur Sachan, Susmit Singha Roy, Gabriela Alva, Ho-yung David Hwang, Uday Mitra, El Mehdi Bazizi, Angada Bangalore Sachid, He Ren, Sushant Mittal
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Patent number: 11437274Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.Type: GrantFiled: September 14, 2020Date of Patent: September 6, 2022Assignee: Micromaterials LLCInventors: Regina Freed, Madhur Sachan, Susmit Singha Roy, Gabriela Alva, Ho-yung David Hwang, Uday Mitra, El Mehdi Bazizi, Angada Bangalore Sachid, He Ren, Sushant Mittal
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Publication number: 20220254886Abstract: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 ?m. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.Type: ApplicationFiled: February 8, 2021Publication date: August 11, 2022Applicant: Applied Materials, Inc.Inventors: Ashish Pal, El Mehdi Bazizi, Siddarth Krishnan, Xing Chen, Lan Yu, Tyler Sherwood
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Publication number: 20220246742Abstract: Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices comprise a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.Type: ApplicationFiled: January 25, 2022Publication date: August 4, 2022Applicant: Applied Materials, Inc.Inventors: Ashish Pal, El Mehdi Bazizi, Benjamin Colombeau, Myungsun Kim
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Publication number: 20220069125Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.Type: ApplicationFiled: November 10, 2021Publication date: March 3, 2022Inventors: IGNASI CORTES, ALBAN ZAKA, TOM HERRMANN, EL MEHDI BAZIZI, RICHARD FRANCIS TAYLOR, III