Abstract: Aspects of the disclosure provide a circuit including a logic circuit. The logic circuit is configured to operate without inputs from a first clock signal. The logic circuit is further configured to frequency-divide the first clock signal to generate a second clock signal based on a logic combination of a first pattern provided by a first circuitry driven by the first clock signal, and a second pattern provided by a second circuitry driven by the first clock signal.

Abstract: Aspects of the disclosure provide a circuit including a logic circuit. The logic circuit is configured to operate without inputs from a first clock signal. The logic circuit is further configured to frequency-divide the first clock signal to generate a second clock signal based on a logic combination of a first pattern provided by a first circuitry driven by the first clock signal, and a second pattern provided by a second circuitry driven by the first clock signal.

Abstract: A method includes receiving, over multiple serial interfaces arranged in parallel to couple between a transmitter and a receiver, a data burst which includes start-of-frame markers and is transmitted over the serial interfaces as multiple respective partial bursts such that each start-of-frame marker is transmitted over the multiple serial interfaces. A relative symbol offset between two or more start-of-frame markers on respective two or more of the serial interfaces is detected at the receiver. The data burst is decoded based on the detected relative symbol offset.