Patents by Inventor Elaine B. Reyes

Elaine B. Reyes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor assembly for improved device warpage and solder ball coplanarity
    Patent number: 7462943
    Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: December 9, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Patricio A Ancheta, Jr., Ramil A Viluan, James R. M. Baello, Elaine B Reyes
  • Semiconductor Assembly for Improved Device Warpage and Solder Ball Coplanarity
    Publication number: 20080142949
    Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.
    Type: Application
    Filed: June 13, 2007
    Publication date: June 19, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Patricio A. Ancheta, Ramil A. Viluan, James R. M. Baello, Elaine B. Reyes
  • Semiconductor assembly for improved device warpage and solder ball coplanarity
    Patent number: 7244636
    Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: July 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Patricio V. Ancheta, Jr., Ramil A. Viluan, James R. M. Baello, Elaine B. Reyes