Patents by Inventor Elard Stein Von Kamienski
Elard Stein Von Kamienski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7755130Abstract: A memory cell array of nonvolatile semiconductor memory cells is specified in which a minority carrier sink is formed within a semiconductor body in the region of the memory cell array, the minority carrier sink being arranged outside a space charge zone structure that forms in the semiconductor body during operation of the semiconductor memory cells, and the minority carrier sink having a shorter minority carrier lifetime in comparison with a semiconductor zone reaching as far as a surface of the semiconductor body.Type: GrantFiled: May 10, 2007Date of Patent: July 13, 2010Assignee: Qimonda AGInventor: Elard Stein Von Kamienski
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Publication number: 20080277717Abstract: A memory cell array of nonvolatile semiconductor memory cells is specified in which a minority carrier sink is formed within a semiconductor body in the region of the memory cell array, the minority carrier sink being arranged outside a space charge zone structure that forms in the semiconductor body during operation of the semiconductor memory cells, and the minority carrier sink having a shorter minority carrier lifetime in comparison with a semiconductor zone reaching as far as a surface of the semiconductor body.Type: ApplicationFiled: May 10, 2007Publication date: November 13, 2008Applicant: QIMONDA AGInventor: Elard Stein Von Kamienski
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Patent number: 7408222Abstract: A charge-trapping device includes a field effect transistor, which has source and drain regions. The source and drain regions have a dopant concentration profile, which has a gradient each in a vertical and a lateral direction with respect to a surface of a semiconductor substrate. The gradient in the lateral direction towards a depletion region of the transistor is larger than the gradient in the vertical direction towards a well region.Type: GrantFiled: March 27, 2006Date of Patent: August 5, 2008Assignee: Infineon Technologies AGInventors: Rainer Hagenbeck, Christoph Ludwig, Mark Isler, Elard Stein von Kamienski
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Patent number: 7151697Abstract: A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector includes a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.Type: GrantFiled: November 30, 2004Date of Patent: December 19, 2006Assignee: Infineon Technologies AGInventors: Stephan Riedel, Elard Stein von Kamienski, Norbert Schulze
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Patent number: 7026220Abstract: The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory layer between confinement layers and the implantation of dopants for bitlines and source/drain regions, an oxidation of semiconductor material to form upper bitline isolation regions takes place. By this method, additional oxide regions are produced at the edges of the memory layer in the same oxidation step. Either a silicon layer may be deposited and reduced to sidewall spacers, which are subsequently oxidized; or recesses are etched into the memory layer and subsequently filled with semiconductor oxide.Type: GrantFiled: December 7, 2004Date of Patent: April 11, 2006Assignee: Infineon Technologies AGInventors: Georg Tempel, Elard Stein von Kamienski, Stephan Riedel, Veronika Polei, Roland Haberkern, Roman Knoefler
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Patent number: 7008849Abstract: A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells disposed at the points at which the bitlines and wordlines cross each other. According to a first aspect of the present invention, the isolating layer is removed from the bitlines at the portions that are not covered by the wordlines, whereas the areas between the bitlines remain unaffected. Alternatively, the isolating layer is removed from the whole cell array. Then, an electrical conductive material is provided on the exposed portions of the bitlines. The method is used to provide bitline contacts in a nitride read only memory (NROM™) chip.Type: GrantFiled: December 1, 2003Date of Patent: March 7, 2006Assignee: Infineon Technologies AGInventors: Grit Schwalbe, Kae-Horng Wang, Klaus Feldner, Elard Stein Von Kamienski
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Publication number: 20040192022Abstract: A semiconductor configuration has an active region, a metalization layer having at least one metal plane, and connecting lines between the active region and the metalization layer. The least one metal plane is embedded in an intermetal dielectric. A UV protection plane is integrated with the metalization layer. A method for fabricating such a semiconductor configuration is also provided.Type: ApplicationFiled: July 1, 2003Publication date: September 30, 2004Inventors: Mirko Vogt, Veronika Polei, Stephan Riedel, Elard Stein Von Kamienski
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Publication number: 20040120198Abstract: A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells disposed at the points at which the bitlines and wordlines cross each other. According to a first aspect of the present invention, the isolating layer is removed from the bitlines at the portions that are not covered by the wordlines, whereas the areas between the bitlines remain unaffected. Alternatively, the isolating layer is removed from the whole cell array. Then, an electrical conductive material is provided on the exposed portions of the bitlines. The method is used to provide bitline contacts in a nitride read only memory (NROM™) chip.Type: ApplicationFiled: December 1, 2003Publication date: June 24, 2004Inventors: Grit Schwalbe, Kae-Horng Wang, Klaus Feldner, Elard Stein Von Kamienski
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Publication number: 20040070025Abstract: An NROM memory cell is of a planar configuration without an additional oxidation being affected for the fabrication of the bit line oxide. The ONO layer is provided as a memory layer and is disposed with a uniform thickness on the semiconductor material of the source and drain regions and of the channel region, so that the ONO layer forms not only the gate dielectric, but also the insulation of the bit lines from the word lines or the gate electrode.Type: ApplicationFiled: April 30, 2003Publication date: April 15, 2004Inventors: Boaz Eitan, Elard Stein Von Kamienski, Stephan Riedel, Assaf Shappir
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Patent number: 6654281Abstract: A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of one-transistor memory cells disposed in a matrix form being driven both via word lines and via bit lines. In this case, each one-transistor memory cell has both a source line and a drain line, as a result of which selective driving of the respective drain and source regions is obtained. In this way, a leakage current in the semiconductor memory device can be optimally reduced with minimal space requirement.Type: GrantFiled: June 20, 2002Date of Patent: November 25, 2003Assignee: Infineon Technologies AGInventors: Georg Georgakos, Kai Huckels, Jakob Kriz, Christoph Kutter, Andreas Liebelt, Christoph Ludwig, Elard Stein von Kamienski, Peter Wawer
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Patent number: 6645812Abstract: A method for producing a non-volatile semiconductor memory cell with a separate tunnel window cell includes the step of forming a tunnel zone in a late implantation step by performing a tunnel implantation with the aid of a tunnel window cell as a mask. The resulting memory cell has a small area requirement and a high number of program/clear cycles.Type: GrantFiled: December 28, 2001Date of Patent: November 11, 2003Assignee: Infineon Technologies AGInventors: Peter Wawer, Oliver Springmann, Konrad Wolf, Olaf Heitzsch, Kai Huckels, Reinhold Rennekamp, Mayk Röhrich, Elard Stein Von Kamienski, Christoph Kutter, Christoph Ludwig
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Publication number: 20030007386Abstract: A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of one-transistor memory cells disposed in a matrix form being driven both via word lines and via bit lines. In this case, each one-transistor memory cell has both a source line and a drain line, as a result of which selective driving of the respective drain and source regions is obtained. In this way, a leakage current in the semiconductor memory device can be optimally reduced with minimal space requirement.Type: ApplicationFiled: June 20, 2002Publication date: January 9, 2003Inventors: Georg Georgakos, Kai Huckels, Jakob Kriz, Christoph Kutter, Andreas Liebelt, Christoph Ludwig, Elard Stein Von Kamienski, Peter Wawer
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Publication number: 20020119626Abstract: A method for producing a non-volatile semiconductor memory cell with a separate tunnel window cell includes the step of forming a tunnel zone in a late implantation step by performing a tunnel implantation with the aid of a tunnel window cell as a mask. The resulting memory cell has a small area requirement and a high number of program/clear cycles.Type: ApplicationFiled: December 28, 2001Publication date: August 29, 2002Inventors: Peter Wawer, Oliver Springmann, Konrad Wolf, Olaf Heitzsch, Kai Huckels, Reinhold Rennekamp, Mayk Rohrich, Elard Stein Von Kamienski, Christoph Kutter, Christoph Ludwig
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Publication number: 20020102799Abstract: EEPROM and FLASH memory cells are formed together in integrated production. A gate finger is used for implementing a homogeneous tunnel diffusion region for the EEPROM memory cell. This allows the different memory cells to be produced in a particularly simple and inexpensive manner.Type: ApplicationFiled: April 16, 2001Publication date: August 1, 2002Inventors: Peter Wawer, Elard Stein Von Kamienski, Christoph Ludwig
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Patent number: 6368970Abstract: A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer on the semiconductor substrate and providing a hard mask on the buffer oxide layer. An STI trench is etched by using the hard mask and a liner oxide layer is provided in the STI trench. The hard mask is removed to expose the buffer oxide layer and the buffer oxide layer is removed by an etching process. The buffer oxide layer is etched more rapidly than the liner oxide layer in the etching process. A gate oxide layer is provided on the semiconductor substrate. A semiconductor configuration is also provided.Type: GrantFiled: August 24, 2000Date of Patent: April 9, 2002Assignee: Infineon Technologies AGInventors: Ayad Abdul-Hak, Achim Gratz, Christoph Ludwig, Reinhold Rennekamp, Elard Stein Von Kamienski, Peter Wawer
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Patent number: 5859464Abstract: An optoelectronic component has an Al.sub.2 O.sub.3 or Si substrate having a surface on which a buried CoSi.sub.2 layer is provided, a Si layer overlying the buried CoSi.sub.2 layer. A metal layer on a portion of this latter Si layer forms a diode between the metal layer, the underlying portion of the Si layer and the buried CoSi.sub.2 layer and a waveguide for a transparent portion of the metal layer delivers photon energy to the underlying portion of the Si layer.Type: GrantFiled: September 26, 1996Date of Patent: January 12, 1999Assignee: Forschungszentrum Julich GmbHInventors: Olaf Hollricher, Frank Ruders, Christoph Buchal, Hartmut Roskos, Jens Peter Hermanns, Elard Stein Von Kamienski, Klaus Rademacher