Patents by Inventor Elbert E. Huang
Elbert E. Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100151638Abstract: A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width.Type: ApplicationFiled: February 25, 2010Publication date: June 17, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Bruce B. Doris, Elbert E. Huang, Sampath Purushothaman, Carl J. Radens
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Patent number: 7696542Abstract: A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width.Type: GrantFiled: January 22, 2008Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Bruce B. Doris, Elbert E. Huang, Sampath Purushothaman, Carl J. Radens
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Patent number: 7598169Abstract: A method to fabricate interconnect structures that are part of integrated circuits and microelectronic devices by utilization of an irradiation to remove and clean a sacrificial material used therein is described. The advantages of utilizing the irradiation to remove the sacrificial material include reduced damage to interlayer dielectric layers that result in enhanced device performance and/or increased reliability.Type: GrantFiled: February 21, 2007Date of Patent: October 6, 2009Assignee: International Business Machines CorporationInventors: Qinghuang Lin, Elbert E. Huang, Christy S. Tyberg, Ronald A. DellaGuardia
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Patent number: 7592685Abstract: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.Type: GrantFiled: August 31, 2007Date of Patent: September 22, 2009Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Publication number: 20090200636Abstract: Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.Type: ApplicationFiled: February 12, 2008Publication date: August 13, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Nicholas C. M. Fuller, David V. Horak, Elbert E. Huang, Wai-Kin Li, Anthony D. Lisi, Satyanarayana V. Nitta, Shom Ponoth
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Publication number: 20090184374Abstract: A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width.Type: ApplicationFiled: January 22, 2008Publication date: July 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Bruce B. Doris, Elbert E. Huang, Sampath Purushothaman, Carl J. Radens
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Publication number: 20090041989Abstract: Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.Type: ApplicationFiled: August 9, 2007Publication date: February 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Timothy J. Dalton, Elbert E. Huang, Sampath Purushothaman, Carl J. Radens
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Patent number: 7470597Abstract: A method of fabricating a structure including a low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer is described herein. The method includes applying a coating of a polymeric preceramic precursor, converting the polymeric preceramic precursor into a low-k sublayer, applying a coating of an air barrier sublayer and exposing the air barrier sublayer to a reactive plasma.Type: GrantFiled: May 2, 2006Date of Patent: December 30, 2008Assignee: International Business Machines CorporationInventors: Jeffrey C. Hedrick, Elbert E. Huang
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Publication number: 20080254612Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, O?y?0.3, 0.05?z?0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.Type: ApplicationFiled: June 17, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Elbert E. Huang, Kaushik A. Kumar, Kelly Malone, Dirk Pfeiffer, Muthumanickam Sankarapandian, Christy S. Tyberg
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Publication number: 20080254614Abstract: Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures are also described. The advantages of utilizing these low-k multilayered dielectric diffusion barrier layer is a gain in chip performance through a reduction in capacitance between conducting metal features and an increase in reliability as the multilayered dielectric diffusion barrier layer are impermeable to air and prevent metal diffusion.Type: ApplicationFiled: June 23, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey C. Hedrick, Elbert E. Huang
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Publication number: 20080254630Abstract: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.Type: ApplicationFiled: June 16, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. EDELSTEIN, Matthew E. Colburn, Edward C. Cooney, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Publication number: 20080200034Abstract: A method to fabricate interconnect structures that are part of integrated circuits and microelectronic devices by utilization of an irradiation to remove and clean a sacrificial material used therein is described. The advantages of utilizing the irradiation to remove the sacrificial material include reduced damage to interlayer dielectric layers that result in enhanced device performance and/or increased reliability.Type: ApplicationFiled: February 21, 2007Publication date: August 21, 2008Inventors: Qinghuang Lin, Elbert E. Huang, Christy S. Tyberg, Ronald A. DellaGuardia
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Patent number: 7405147Abstract: A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column.Type: GrantFiled: January 30, 2004Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Patent number: 7396758Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, 0?y?0.3, 0.05?z?0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.Type: GrantFiled: January 3, 2007Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Elbert E. Huang, Kaushik A. Kumar, Kelly Malone, Dirk Pfeiffer, Muthumanickam Sankarapandian, Christy S. Tyberg
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Publication number: 20080128766Abstract: A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.Type: ApplicationFiled: February 14, 2008Publication date: June 5, 2008Applicant: International Business Machines CorporationInventors: Elbert E. Huang, Philip J. Oldiges, Ghavam G. Shahidi, Christy S. Tyberg, Xinlin Wang, Robert L. Wisnieff
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Patent number: 7365378Abstract: A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.Type: GrantFiled: March 31, 2005Date of Patent: April 29, 2008Assignee: International Business Machines CorporationInventors: Elbert E. Huang, Philip J. Oldiges, Ghavam G. Shahidi, Christy S. Tyberg, Xinlin Wang, Robert L. Wisnieff
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Patent number: 7326442Abstract: An antireflective composition and a lithographic structure comprising a silicon-metal oxide, antireflective material derived from the composition. The antireflective composition comprises a polymer of formula I, wherein 1?x?2; 1?y?5; 1?0; m>0; n>0; R is a chromophore, M is a metal selected from Group IIIB to Group VIB, lanthanides, Group IIIA, Group IVA except silicon; and L is an optional ligand. The invention is also directed to a process of making a lithographic structure including a silicon-metal oxide, antireflective material.Type: GrantFiled: July 14, 2005Date of Patent: February 5, 2008Assignee: International Business Machines CorporationInventors: Katherina E. Babich, Sean D. Burns, Elbert E. Huang, Arpan P. Mahorowala, Dirk Pfeiffer, Karen Temple
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Patent number: 7256146Abstract: The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz, where 0.1?v?0.9, 0?w?0.5, 0.01?x?0.9, 0?y?0.7, 0.01?z?0.8 for v+w+x+y+z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1<v<0.8, 0<w<0.8, 0.05<x<0.8, 0<y<0.3, 0.05<z<0.8 for v+w+x+y+z=1 and then converting the polymeric preceramic layer into a ceramic diffusion barrier by thermal methods.Type: GrantFiled: May 13, 2005Date of Patent: August 14, 2007Assignee: International Business Machines CorporationInventors: Stephan A. Cohen, Stephen McConnell Gates, Jeffrey C. Hedrick, Elbert E. Huang, Dirk Pfeiffer
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Patent number: 7187081Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, 0?y?0.3, 0.05?z?0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.Type: GrantFiled: October 31, 2003Date of Patent: March 6, 2007Assignee: International Business Machines CorporationInventors: Elbert E. Huang, Kaushik A. Kumar, Kelly Malone, Dirk Pfeiffer, Muthumanickam Sankarapandian, Christy S. Tyberg
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Patent number: 7081673Abstract: Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures are also described. The advantages of utilizing these low-k multilayered dielectric diffusion barrier layer is a gain in chip performance through a reduction in capacitance between conducting metal features and an increase in reliability as the multilayered dielectric diffusion barrier layer are impermeable to air and prevent metal diffusion.Type: GrantFiled: August 27, 2003Date of Patent: July 25, 2006Assignee: International Business Machines CorporationInventors: Jeffrey C. Hedrick, Elbert E. Huang