Abstract: A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source.

Abstract: A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source.

Abstract: A differential sensing content addressable memory cell without any word lines connected to the cells in the same row comprises a first bit line for supplying a first bit. A first storage element has a first phase change resistor for storing a first stored bit, which is connected in series with a first diode. The first storage element is connected to the first bit line. A second bit line supplies a second bit, with the second bit being an inverse of the first bit. A second storage element has a second phase change resistor for storing a second stored bit, which is connected in series with a second diode. The second storage element is connected to the second bit line.

Abstract: A non-volatile memory semiconductor device has a circuit to compensate for the variation in the data pattern to be programmed. The variation in the data patter creates a variation in the current requirement. The array receives a plurality of data pattern signals which affect the total amount of current flowing into a plurality of columns and into the memory array. A high voltage source generates an output which is supplied along a conducting path connected to the group of columns. A pass transistor is in the conducting path controlling the current flow in the conducting path. A current source has a first terminal and a second terminal with the first terminal connected to the output of the high voltage generator and the second terminal connected to the gate of the pass transistor. A plurality of current sources are collectively connected to a node.

Abstract: A non-volatile memory semiconductor device has a circuit to compensate for the variation in the data pattern to be programmed. The variation in the data patter creates a variation in the current requirement. The array receives a plurality of data pattern signals which affect the total amount of current flowing into a plurality of columns and into the memory array. A high voltage source generates an output which is supplied along a conducting path connected to the group of columns. A pass transistor is in the conducting path controlling the current flow in the conducting path. A current source has a first terminal and a second terminal with the first terminal connected to the output of the high voltage generator and the second terminal connected to the gate of the pass transistor. A plurality of current sources are collectively connected to a node.