Abstract: An RF device (12), such as an amplifier, is tested by applying a digitally-modulated RF stimulus signal, having a known magnitude and phase angle, to the device to cause it to generate a response signal. The response signal of the device is down-converted and digitized prior to establishing its magnitude and phase angle. The magnitude and phase angle of the digitized, down-converted response signal are compared to the magnitude and phase angle, respectively, of the digitally-modulated stimulus signal to yield transfer functions indicative of the operation of the device.

Abstract: Pseudo-exhaustive self-testing of an electronic circuit (10), containing groups of combinational elements (14.sub.1,14.sub.2, 14.sub.3 . . . 14.sub.n), is accomplished by first partitioning the groups of combinational elements into sub-cones having no more than w inputs each by designating appropriate nodes ("test points") in each cone as the output of a sub-cone. A set of test vectors {a.sub.1, a.sub.2 . . . a.sub.w, b.sub.1, b.sub.2 . . . b.sub.w } is then generated (via an internal generator 74) such that when the vectors are applied to the sub-cones (14.sub.1.sbsb.a, 14.sub.1.sbsb.b . . . . 14.sub.i.sbsb.j), each sub-cone will be exhaustively tested. Each of the inputs of the sub-cones is assigned to receive a vector such that the vectors received at the inputs are linearly independent. The subset of vectors is applied through each of a plurality of pseudo-exhaustive self-test (PEST) flip-flop circuits (88) and through the test points to test the circuit.

Abstract: Compaction of the response signals produced by separate sets of sub-circuits (12.sub.i) within a digital circuit (10) under test is accomplished by first analyzing each response signal produced by a corresponding set of sub-circuits (by way of a logic analyzer (16,18)) to determine if the response signal has a particular pattern. A pattern bit is then set in accordance with the response signal which has the particular pattern. The pattern bits are then compacted by a set of daisy-chained time compactors (20), each compactor serving to exclusively OR the pattern bit from a corresponding logic analyzer (16,18) with a compacted bit generated previously by an upstream compactor.

Abstract: Psuedo-exhaustive self-testing of an electronic circuit (10), containing groups of combinational elements (14.sub.1, 14.sub.2, 14.sub.3 . . . 14.sub.n), is accomplished by first partitioning the groups of combinational elements into sub-cones having no more than w imputs each by designating appropriate nodes ("test points") in each cone as the output of a sub-cone. A set of test vectors {a.sub.1, a.sub.2 . . . a.sub.w, b.sub.1, b.sub.2 . . . b.sub.w } is then generated (via an internal generator 74) such that when the vectors are applied to the sub-cones (14.sub.1.sbsb.a, 14.sub.1.sbsb.b . . . . 14.sub.i.sbsb.j), each sub-cone will be exhaustively tested. Each of the inputs of the sub-cones is assigned to receive a vector such that the vectors received at the inputs are linearly independent. The subset of vectors is applied through each of a plurality of pseudo-exhaustive self-test (PEST) flip-flop circuits (88) and through the test points to test the circuit.