Abstract: A signal cable for an AC-coupled link, may include: a signal conductor; a dielectric surrounding the signal conductor; and a ground sheath having a conductive layer disposed at least partially around the conductor such that the dielectric is positioned between the ground sheath and the signal conductor, wherein the conductive layer comprises a first portion extending in a first direction along the cable and a second portion extending in a second direction, opposite the first direction, along the cable and further wherein the first and second portions of the conductive layer are separated from each other by a gap, the gap being dimensioned to provide a determined amount of capacitance in series in the ground sheath. The gap may form a complete separation between the first and second portions of the conductive layer.

Abstract: A signal cable for an AC-coupled link, may include: a signal conductor; a dielectric surrounding the signal conductor; and a ground sheath having a conductive layer disposed at least partially around the conductor such that the dielectric is positioned between the ground sheath and the signal conductor, wherein the conductive layer comprises a first portion extending in a first direction along the cable and a second portion extending in a second direction, opposite the first direction, along the cable and further wherein the first and second portions of the conductive layer are separated from each other by a gap, the gap being dimensioned to provide a determined amount of capacitance in series in the ground sheath. The gap may form a complete separation between the first and second portions of the conductive layer.

Abstract: Systems and methods are provided for implementing forward error correction (FEC) on data transferred on a data link on the physical layer. Binary encoding can be done in accordance with a physical unit (phit) FEC format. The phit FEC format allows for correction of two bit errors and comprises a codeword having a variable bit size. Pre-coding the phit enables burst errors associated with the link to converted into bit errors. The data can be transmitted in the phit FEC format to a receiving PHY. The correctable two bit errors at one or more locations within the phit FEC format can then be corrected by decoding at the receiving PHY in accordance with the phit FEC. The FEC techniques can minimize latency in the PHY.

Abstract: Systems and methods are provided for implementing forward error correction (FEC) on data transferred on a data link on the physical layer. Binary encoding can be done in accordance with a physical unit (phit) FEC format. The phit FEC format allows for correction of two bit errors and comprises a codeword having a variable bit size. Pre-coding the phit enables burst errors associated with the link to converted into bit errors. The data can be transmitted in the phit FEC format to a receiving PHY. The correctable two bit errors at one or more locations within the phit FEC format can then be corrected by decoding at the receiving PHY in accordance with the phit FEC. The FEC techniques minimize latency in the PHY, being optimal for Gen-Z systems. The FEC techniques can provide improvements over existing FEC schemes that employ large code word sizes and experience high latency.

Abstract: A multiple-layer circuit board has a signaling layer plane, an exterior layer plane, and a ground layer plane. A pair of differential signal lines implemented as strip-lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. A dual slot common mode noise filter may be etched within the ground layer and may include a first U-shaped etching pair comprising a first U-shaped etching and a second U-shaped etching opposing the first U-shaped etching within the ground layer plane.

Abstract: A signal cable for an AC-coupled link, may include: a signal conductor; a dielectric surrounding the signal conductor; and a ground sheath having a conductive layer disposed at least partially around the conductor such that the dielectric is positioned between the ground sheath and the signal conductor, wherein the conductive layer comprises a first portion extending in a first direction along the cable and a second portion extending in a second direction, opposite the first direction, along the cable and further wherein the first and second portions of the conductive layer are separated from each other by a gap, the gap being dimensioned to provide a determined amount of capacitance in series in the ground sheath. The gap may form a complete separation between the first and second portions of the conductive layer.

Abstract: A printed circuit board (PCB) may include a signal layer having a functional region and a PCB signal layer testing region. The PCB signal layer testing region may include a first differential pair having a first length formed on the signal layer, a second differential pair having a second length, different than the first length, formed on the signal layer and a third differential pair having a third length, different than the first length and different than the second length, formed on the signal layer.

Abstract: A system may include an input engine and a void avoidance engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a first net and a second net in the electronic circuit design. The void avoidance engine may perform a void avoidance verification scan to determine whether the first net, the second net, or both, are within a threshold distance from any voids in the electronic circuit design. The void avoidance engine may also generate a double violation alert responsive to a determination that the first net and the second net are both within the threshold distance from a particular void in the electronic circuit design and that the first net and the second net are located on different sides of the same plane of the electronic circuit design.

Abstract: A multiple-layer circuit board has a signaling layer plane, an exterior layer plane, and a ground layer plane. A pair of differential signal lines implemented as strip-lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. A dual slot common mode noise filter may be etched within the ground layer and may include a first U-shaped etching pair comprising a first U-shaped etching and a second U-shaped etching opposing the first U-shaped etching within the ground layer plane.

Abstract: A printed circuit board (PCB) may include a signal layer having a functional region and a PCB signal layer testing region. The PCB signal layer testing region may include a first differential pair having a first length formed on the signal layer, a second differential pair having a second length, different than the first length, formed on the signal layer and a third differential pair having a third length, different than the first length and different than the second length, formed on the signal layer.

Abstract: A multiple-layer circuit board has a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. An element conductively extends inwards from the exterior layer. A void of a defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the EMI propagated by the strip lines. A resistive material of the defected ground structure along a perimeter of the void improves suppression of the EMI propagated by the strip lines, via the resistive material absorbing the EMI.

Abstract: Examples describe a system that may include an input engine and a proximity verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool, may identify a particular signal net and a particular power net the particular signal net is referenced to in the electronic circuit design. The input engine may further identify a particular signal via in the electronic circuit design corresponding to the particular signal net and power vias in the electronic circuit design corresponding to the particular power net. In such examples, the proximity verification engine may also verify that the particular signal via is within a threshold distance from at least one of the power vias and generate a proximity alert in response to a determination that none of the power vias are within the threshold distance from the particular signal via.

Abstract: Examples described herein include an electromagnetic interference shield. In some examples, the electromagnetic interference shield includes a wall comprised of a conductive material. The wall may have a first surface, a second surface, and a thickness between the first surface and the second surface. The shield may include a rounded opening in the wall that creates an air passageway through the thickness of the wall. The shield may also include a first obstruction in the opening and a second obstruction in the opening. The first obstruction may span across the opening. The second obstruction may span across the opening and intersect the first obstruction. The first obstruction and the second obstruction may be waveguide structures.

Abstract: A multiple-layer circuit board has a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. An element conductively extends inwards from the exterior layer. A void of a defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the EMI propagated by the strip lines. A resistive material of the defected ground structure along a perimeter of the void improves suppression of the EMI propagated by the strip lines, via the resistive material absorbing the EMI.

Abstract: A system may include an input engine and a symmetry verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a particular net in the electronic circuit design. The a symmetry verification engine may identify a pair of differential signal vias in the electronic circuit design corresponding to the particular net and determine a verification area surrounding the pair of differential signal vias. The symmetry verification engine may also verify that a particular ground via within the verification area satisfies symmetry criteria with respect to the pair of differential signal vias.

Abstract: Examples describe a system that may include an input engine and a proximity verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool, may identify a particular signal net and a particular power net the particular signal net is referenced to in the electronic circuit design. The input engine may further identify a particular signal via in the electronic circuit design corresponding to the particular signal net and power vias in the electronic circuit design corresponding to the particular power net. In such examples, the proximity verification engine may also verify that the particular signal via is within a threshold distance from at least one of the power vias and generate a proximity alert in response to a determination that none of the power vias are within the threshold distance from the particular signal via.

Abstract: A system may include an input engine and a symmetry verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a particular net in the electronic circuit design. The a symmetry verification engine may identify a pair of differential signal vias in the electronic circuit design corresponding to the particular net and determine a verification area surrounding the pair of differential signal vias. The symmetry verification engine may also verify that a particular ground via within the verification area satisfies symmetry criteria with respect to the pair of differential signal vias.

Abstract: A system may include an input engine and a void avoidance engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a first net and a second net in the electronic circuit design. The void avoidance engine may perform a void avoidance verification scan to determine whether the first net, the second net, or both, are within a threshold distance from any voids in the electronic circuit design. The void avoidance engine may also generate a double violation alert responsive to a determination that the first net and the second net are both within the threshold distance from a particular void in the electronic circuit design and that the first net and the second net are located on different sides of the same plane of the electronic circuit design.

Abstract: Examples described herein include an electromagnetic interference shield. In some examples, the electromagnetic interference shield includes a wall comprised of a conductive material. The wall may have a first surface, a second surface, and a thickness between the first surface and the second surface. The shield may include a rounded opening in the wall that creates an air passageway through the thickness of the wall. The shield may also include a first obstruction in the opening and a second obstruction in the opening. The first obstruction may span across the opening. The second obstruction may span across the opening and intersect the first obstruction. The first obstruction and the second obstruction may be waveguide structures.