Patents by Inventor Elene Terry
Elene Terry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9747225Abstract: An interrupt controller includes a fabric slave that can receive MMIO operation requests, a plurality of output interrupt lines, a plurality of interrupt registers with each interrupt register corresponding to an output interrupt line, a MMIO routing circuit in communication with the fabric slave and the interrupt registers, a plurality of input interrupt lines for receiving line interrupts, and a line interrupt routing circuit in communication with the input interrupt lines and the interrupt registers. The interrupt registers store data for an interrupt that serves as an indication of the source of the interrupt and/or what task(s) need to be done for the interrupt.Type: GrantFiled: May 5, 2015Date of Patent: August 29, 2017Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga Ozguner, Robert Allen Shearer, Elene Terry, Jonathan Ross
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Publication number: 20170171433Abstract: A timing control system includes one or more device processors operatively coupled to one or more devices, a counter connected to the device processor(s), and a plurality of timing registers operatively coupled to the counter, each of the timing registers configured to store a value indicating a time at which an event is to be initiated at a corresponding one of the device(s). The system also includes a pulse generator operatively coupled to the counter and the timing registers, the pulse generator configured to generate one or more associated general-purpose input/output (GPIO) output signals, and send to each of the one or more devices an associated GPIO output signal to initiate the event at a plurality of the one or more devices in coordination with one another or to initiate the event at one of the one or more devices in coordination with another event at that device.Type: ApplicationFiled: December 2, 2016Publication date: June 15, 2017Applicant: Microsoft Technology Licensing, LLCInventors: Jonathan Ross, Robert Allen Shearer, Elene Terry
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Patent number: 9588902Abstract: A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and the page table block base address are combined to locate a page table entry, wherein the page table entry includes a physical memory page base address and a size of the physical memory page is indicated by the native page table size field. The access offset and the physical memory page base address are combined to determine the physical memory address.Type: GrantFiled: December 4, 2012Date of Patent: March 7, 2017Assignees: Advanced Micro Devices, Inc., ATI Technologies, ULCInventors: Elene Terry, Dhirendra Partap Singh Rana
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Patent number: 9549100Abstract: A timing control system includes one or more device processors operatively coupled to one or more devices, a counter connected to the device processor(s), and a plurality of timing registers operatively coupled to the counter, each of the timing registers configured to store a value indicating a time at which an event is to be initiated at a corresponding one of the device(s). The system also includes a pulse generator operatively coupled to the counter and the timing registers, the pulse generator configured to generate one or more associated general-purpose input/output (GPIO) output signals, and send to each of the one or more devices an associated GPIO output signal to initiate the event at a plurality of the one or more devices in coordination with one another or to initiate the event at one of the one or more devices in coordination with another event at that device.Type: GrantFiled: April 23, 2015Date of Patent: January 17, 2017Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Jonathan Ross, Robert Allen Shearer, Elene Terry
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Publication number: 20160328339Abstract: An interrupt controller includes a fabric slave that can receive MMIO operation requests, a plurality of output interrupt lines, a plurality of interrupt registers with each interrupt register corresponding to an output interrupt line, a MMIO routing circuit in communication with the fabric slave and the interrupt registers, a plurality of input interrupt lines for receiving line interrupts, and a line interrupt routing circuit in communication with the input interrupt lines and the interrupt registers. The interrupt registers store data for an interrupt that serves as an indication of the source of the interrupt and/or what task(s) need to be done for the interrupt.Type: ApplicationFiled: May 5, 2015Publication date: November 10, 2016Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga Ozguner, Robert Allen Shearer, Elene Terry, Jonathan Ross
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Publication number: 20160316110Abstract: A timing control system includes one or more device processors operatively coupled to one or more devices, a counter connected to the device processor(s), and a plurality of timing registers operatively coupled to the counter, each of the timing registers configured to store a value indicating a time at which an event is to be initiated at a corresponding one of the device(s). The system also includes a pulse generator operatively coupled to the counter and the timing registers, the pulse generator configured to generate one or more associated general-purpose input/output (GPIO) output signals, and send to each of the one or more devices an associated GPIO output signal to initiate the event at a plurality of the one or more devices in coordination with one another or to initiate the event at one of the one or more devices in coordination with another event at that device.Type: ApplicationFiled: April 23, 2015Publication date: October 27, 2016Inventors: Jonathan Ross, Robert Allen Shearer, Elene Terry
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Patent number: 8797332Abstract: Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.Type: GrantFiled: December 14, 2011Date of Patent: August 5, 2014Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Paul Blinzer, Leendert Van Doorn, Gongxian Jeffrey Cheng, Elene Terry, Thomas Woller, Arshad Rahman
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Publication number: 20140156968Abstract: A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and the page table block base address are combined to locate a page table entry, wherein the page table entry includes a physical memory page base address and a size of the physical memory page is indicated by the native page table size field. The access offset and the physical memory page base address are combined to determine the physical memory address.Type: ApplicationFiled: December 4, 2012Publication date: June 5, 2014Applicants: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.Inventors: Elene Terry, Dhirendra Partap Singh Rana
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Patent number: 8578129Abstract: In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.Type: GrantFiled: December 14, 2011Date of Patent: November 5, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Paul Blinzer, Leendert Peter Van Doorn, Gongxian Jeffrey Cheng, Elene Terry, Thomas Roy Woller, Arshad Rahman
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Patent number: 8489752Abstract: A system and method for controlling communications between a plurality of clients and a central component. An embodiment of the invention includes one or more buses that connect the clients and the central component. This embodiment also includes a control module that is configured to receive ASK messages from the clients and issue GO commands to the clients. Each ASK message represents a request from a client to access the central component. Each GO command to the client represents permission for that client to access the central component. The control module comprises delay stages that delay the GO command. The delays may be different from client to client. The number of delay stages is chosen so that for all clients, the delay between the issuance of a GO command and the receipt at the central component of communications from the clients is the same.Type: GrantFiled: May 29, 2009Date of Patent: July 16, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Warren Kruger, Zohair Hyder, Elene Terry, Xidong Wang
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Publication number: 20130159664Abstract: In a CPU of the combined CPU/APD architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to an APD, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address conType: ApplicationFiled: December 14, 2011Publication date: June 20, 2013Inventors: Paul BLINZER, Leendert Peter Van Doorn, Gongxian Jeffrey Cheng, Elene Terry, Thomas Roy Woller, Arshad Rahman
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Publication number: 20120162234Abstract: Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.Type: ApplicationFiled: December 14, 2011Publication date: June 28, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Paul Blinzer, Leendert Van Doorn, Gongxian Jeffrey Cheng, Elene Terry, Thomas Woller, Arshad Rahman
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Publication number: 20090313323Abstract: A system and method for controlling communications between a plurality of clients and a central component. An embodiment of the invention includes one or more buses that connect the clients and the central component. This embodiment also includes a control module that is configured to receive ASK messages from the clients and issue GO commands to the clients. Each ASK message represents a request from a client to access the central component. Each GO command to the client represents permission for that client to access the central component. The control module comprises delay stages that delay the GO command. The delays may be different from client to client. The number of delay stages is chosen so that for all clients, the delay between the issuance of a GO command and the receipt at the central component of communications from the clients is the same.Type: ApplicationFiled: May 29, 2009Publication date: December 17, 2009Applicant: Advanced Micro Devices, Inc.Inventors: Warren Kruger, Zohair Hyder, Elene Terry, Xidong Wang