Patents by Inventor Eleonora Franchi Scarselli
Eleonora Franchi Scarselli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12211582Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A switching circuit is connected between each bit line and a corresponding column output. The switching circuit is controlled to turn on to generate the analog signal dependent on the computational weight and for a time duration controlled by the coefficient data signal. A column combining circuit combines (by addition and/or subtraction) and integrates analog signals at the column outputs of the biasing circuits. The addition/subtraction is dependent on one or more a sign of the coefficient data and a sign of the computational weight and may further implement a binary weighting function.Type: GrantFiled: April 12, 2022Date of Patent: January 28, 2025Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Marcella Carissimi, Alessio Antolini, Eleonora Franchi Scarselli, Antonio Gnudi, Andrea Lico
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Patent number: 11942144Abstract: A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.Type: GrantFiled: January 24, 2022Date of Patent: March 26, 2024Assignees: STMicroelectronics S.r.l., Alma Mater Studiorum—Universita' Di BolognaInventors: Marco Pasotti, Marcella Carissimi, Antonio Gnudi, Eleonora Franchi Scarselli, Alessio Antolini, Andrea Lico
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Publication number: 20240056060Abstract: A circuit includes a clock input node, a first signal input node configured to receive a first modulated signal switching between a first DC voltage and a second DC voltage, a bias circuit, a first output node, a first capacitor, a second capacitor, and switching circuitry coupled to the first capacitor and the second capacitor. Control circuitry is configured to initially set the switching circuitry in a first configuration in response to the first modulated signal having the second DC voltage, thereby charging the first capacitor to the second DC voltage and charging the second capacitor to the first DC voltage, and subsequently set the switching circuitry in a second configuration in response to an edge detected in the clock signal, thereby producing the first threshold voltage at the first output node after charge redistribution taking place between the first and second capacitors.Type: ApplicationFiled: July 26, 2023Publication date: February 15, 2024Inventors: Matteo D'Addato, Alessia Maria Elgani, Luca Perilli, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Antonio Canegallo, Giulio Ricotti
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Patent number: 11894052Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.Type: GrantFiled: April 12, 2022Date of Patent: February 6, 2024Assignees: STMicroelectronics S.r.l., Alma Mater Studiorum—Universita' Di BolognaInventors: Marco Pasotti, Marcella Carissimi, Alessio Antolini, Eleonora Franchi Scarselli, Antonio Gnudi, Andrea Lico, Paolo Romele
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Publication number: 20230326524Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.Type: ApplicationFiled: April 12, 2022Publication date: October 12, 2023Applicants: STMicroelectronics S.r.l., Alma Mater Studiorum - Universita' Di BolognaInventors: Marco PASOTTI, Marcella CARISSIMI, Alessio ANTOLINI, Eleonora FRANCHI SCARSELLI, Antonio GNUDI, Andrea LICO, Paolo ROMELE
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Publication number: 20230326499Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A switching circuit is connected between each bit line and a corresponding column output. The switching circuit is controlled to turn on to generate the analog signal dependent on the computational weight and for a time duration controlled by the coefficient data signal. A column combining circuit combines (by addition and/or subtraction) and integrates analog signals at the column outputs of the biasing circuits. The addition/subtraction is dependent on one or more a sign of the coefficient data and a sign of the computational weight and may further implement a binary weighting function.Type: ApplicationFiled: April 12, 2022Publication date: October 12, 2023Applicants: STMicroelectronics S.r.l., Alma Mater Studiorum - Universita' Di BolognaInventors: Marco PASOTTI, Marcella CARISSIMI, Alessio ANTOLINI, Eleonora FRANCHI SCARSELLI, Antonio GNUDI, Andrea LICO
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Publication number: 20230318532Abstract: In accordance with an embodiment, an envelope detector includes a first transistor having a first current conduction terminal coupled to a first connection node; a second current conduction terminal coupled to an intermediate node; and a control terminal coupled the signal input node and to a biasing node; a second transistor having a first current conduction terminal coupled to the intermediate node; a second current conduction terminal coupled to a second connection node; and a control terminal coupled to the biasing node; and a first temperature compensating transistor that is diode-connected and coupled between a compensation output node and the biasing node. The second connection node is coupled to the compensation output node and the first connection node is coupled to a detector output.Type: ApplicationFiled: March 28, 2023Publication date: October 5, 2023Inventors: Alessia Maria Elgani, Matteo D'Addato, Luca Perilli, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Antonio Canegallo, Giulio Ricotti
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Publication number: 20230238055Abstract: A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.Type: ApplicationFiled: January 24, 2022Publication date: July 27, 2023Applicants: STMicroelectronics S.r.l., Alma Mater Studiorum - Universita' Di BolognaInventors: Marco PASOTTI, Marcella CARISSIMI, Antonio GNUDI, Eleonora FRANCHI SCARSELLI, Alessio ANTOLINI, Andrea LICO
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Patent number: 11342885Abstract: In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.Type: GrantFiled: November 27, 2019Date of Patent: May 24, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Alessia Maria Elgani, Francesco Renzini, Luca Perilli, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Canegallo, Giulio Ricotti
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Publication number: 20200177133Abstract: In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.Type: ApplicationFiled: November 27, 2019Publication date: June 4, 2020Inventors: Alessia Maria Elgani, Francesco Renzini, Luca Perilli, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Canegallo, Giulio Ricotti
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Patent number: 9176185Abstract: A testing apparatus includes a tester and a probe card system that includes a probe card connected to the tester, and an active interposer connected to the probe card and wirelessly coupled with a device to be tested. The active interposer includes pads positioned on its free surface facing the device. The pads are positioned with respect to pads of the device so that each pad of the active interposer faces a pad of the device and is separated therefrom by a dielectric. Each pair of facing pads forms an elementary wireless coupling element which allows a wireless transmission between the active interposer and the device. The active interposer also includes an amplifier circuit configured to amplify wireless signals from the device before forwarding them to the tester. The probe card system includes a transmission element able to transmit a power voltage from the tester to the device.Type: GrantFiled: July 25, 2012Date of Patent: November 3, 2015Assignee: STMicroelectronics S.r.l.Inventors: Roberto Canegallo, Mauro Scandiuzzo, Roberto Cardu, Eleonora Franchi Scarselli, Alberto Pagani
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Patent number: 9147636Abstract: A method includes communicatively coupling first and second integrated electronic devices together through a plurality of reference capacitors, transmitting a plurality of transmission reference signals on transmission reference electrodes of the plurality of reference capacitors, receiving coupling signals on reception reference electrodes of the plurality of reference capacitors, amplifying said coupling signals, generating a plurality of reception reference signals, generating a plurality of reception control signals as a function of the plurality of reception reference signals, and detecting a possible misalignment between said first and second integrated electronic devices based on the plurality of reception control signals.Type: GrantFiled: November 14, 2011Date of Patent: September 29, 2015Assignee: STMicroelectronics S.r.l.Inventors: Roberto Canegallo, Mauro Scandiuzzo, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Guerrieri
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Publication number: 20130027071Abstract: A testing apparatus includes a tester and a probe card system that includes a probe card connected to the tester, and an active interposer connected to the probe card and wirelessly coupled with a device to be tested. The active interposer includes pads positioned on its free surface facing the device. The pads are positioned with respect to pads of the device so that each pad of the active interposer faces a pad of the device and is separated therefrom by a dielectric. Each pair of facing pads forms an elementary wireless coupling element which allows a wireless transmission between the active interposer and the device. The active interposer also includes an amplifier circuit configured to amplify wireless signals from the device before forwarding them to the tester. The probe card system includes a transmission element able to transmit a power voltage from the tester to the device.Type: ApplicationFiled: July 25, 2012Publication date: January 31, 2013Applicant: STMicroelectonics S.r.I.Inventors: Roberto Canegallo, Mauro Scandiuzzo, Roberto Cardu, Eleonora Franchi Scarselli, Alberto Pagani
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Publication number: 20130001547Abstract: A method includes communicatively coupling first and second integrated electronic devices together through a plurality of reference capacitors, transmitting a plurality of transmission reference signals on transmission reference electrodes of the plurality of reference capacitors, receiving coupling signals on reception reference electrodes of the plurality of reference capacitors, amplifying said coupling signals, generating a plurality of reception reference signals, generating a plurality of reception control signals as a function of the plurality of reception reference signals, and detecting a possible misalignment between said first and second integrated electronic devices based on the plurality of reception control signals.Type: ApplicationFiled: November 14, 2011Publication date: January 3, 2013Applicant: STMICROELECTRONICS S.R.L.Inventors: Roberto Canegallo, Mauro Scandiuzzo, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Guerrieri
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Patent number: 8340576Abstract: A device and method to compensate for distortions of amplitude that afflict systems for communicating through capacitive coupling. A circuit includes a first transmitter stage, a first receiver stage, and a first coupling capacitor, coupled between the first transmitter stage and the first receiver stage. The first receiver stage includes a calibration amplifier of a variable-gain type coupled between the first coupling capacitor and an output of the electronic circuit. The electronic circuit includes a reference channel formed by: a transmission calibration stage; a reception calibration stage; and a reference capacitor coupled between the transmission calibration stage and the reception calibration stage.Type: GrantFiled: June 29, 2010Date of Patent: December 25, 2012Assignee: STMicroelectronics S.r.l.Inventors: Roberto Canegallo, Mauro Scandiuzzo, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Guerrieri, Federico Natali
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Patent number: 8150315Abstract: A method for verifying alignment between first and second integrated devices coupled together using a reference and a coupling capacitor, including: transmitting a reference signal on a transmission electrode of the reference capacitor; receiving a coupling signal on a reception electrode of the reference capacitor; amplifying the coupling signal, generating a reception reference signal; generating a reception control signal as a function of the reception reference signal; transmitting a communication signal on an electrode of the coupling capacitor; receiving a reception signal on an electrode of the coupling capacitor; amplifying the reception signal, generating a first compensated signal; controlling a level of amplification of amplifying the coupling signal and the reception signal as a function of the reception control signal; and detecting a possible misalignment between the first and second devices based on an amplitude of the communication signal and an amplitude of the compensated signal.Type: GrantFiled: June 29, 2010Date of Patent: April 3, 2012Assignee: STMicroelectronics S.r.l.Inventors: Roberto Canegallo, Mauro Scandiuzzo, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Guerrieri
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Publication number: 20110319015Abstract: A method for verifying alignment between first and second integrated devices coupled together using a reference and a coupling capacitor, including: transmitting a reference signal on a transmission electrode of the reference capacitor; receiving a coupling signal on a reception electrode of the reference capacitor; amplifying the coupling signal, generating a reception reference signal; generating a reception control signal as a function of the reception reference signal; transmitting a communication signal on an electrode of the coupling capacitor; receiving a reception signal on an electrode of the coupling capacitor; amplifying the reception signal, generating a first compensated signal; controlling a level of amplification of amplifying the coupling signal and the reception signal as a function of the reception control signal; and detecting a possible misalignment between the first and second devices based on an amplitude of the communication signal and an amplitude of the compensated signal.Type: ApplicationFiled: June 29, 2010Publication date: December 29, 2011Applicant: STMICROELECTRONICS S.R.L.Inventors: Roberto Canegallo, Mauro Scandiuzzo, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Guerrieri
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Publication number: 20110319014Abstract: A device and method to compensate for distortions of amplitude that afflict systems for communicating through capacitive coupling. A circuit includes a first transmitter stage, a first receiver stage, and a first coupling capacitor, coupled between the first transmitter stage and the first receiver stage. The first receiver stage includes a calibration amplifier of a variable-gain type coupled between the first coupling capacitor and an output of the electronic circuit. The electronic circuit includes a reference channel formed by: a transmission calibration stage; a reception calibration stage; and a reference capacitor coupled between the transmission calibration stage and the reception calibration stage.Type: ApplicationFiled: June 29, 2010Publication date: December 29, 2011Applicant: STMICROELECTRONICS S.R.L.Inventors: Roberto Canegallo, Mauro Scandiuzzo, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Guerrieri, Federico Natali