Abstract: The correlation and demodulation circuit (6) in particular for a pseudo-random code radio-frequency signal receiver (1) includes a correlation stage (7) connected to a microprocessor (12) in particular for configuring the correlation stage in normal operating mode or in test mode. In normal operation the stage receives intermediate signals (IF) corresponding to the radio-frequency signals shaped in means (3) for receiving the modulated signals from the receiver. The intermediate signals are correlated in a correlator control loop (8) of said correlation stage (7) with a replica of the first code supplied by a code generator (25). The code generator (25) is adapted via a microprocessor (12) to generate a replica of a pseudo-random code of shorter repetition length than the pseudo-random code of the radio-frequency signals.

Abstract: A low power RF receiver (1) has an antenna (2), a reception and shaping stage (3) for the radio-frequency signals provided by the antenna, a 12-channel correlation stage (7) receiving intermediate signals (IF) shaped by the reception stage (3), and a microprocessor (12) connected to the correlation stage for calculating X, Y and Z position, velocity and time data as a function of data provided by the radio-frequency signals, such as GPS signals, transmitted by satellites. Each channel includes a correlator (8) associated with a controller (9), which also includes a digital signal processing algorithm to allow all the synchronisation tasks for acquiring and tracking a satellite to be performed autonomously when the channel (7?) is set in operation, and to lock onto the satellite. Buffer registers (11) are placed at the interface between the correlation stage (7) and the microprocessor (12) for the mutual transfer of data.

Abstract: The numerically controlled oscillator (8) is mounted in particular in a radiofrequency signal receiver which further includes means (3) for receiving and shaping the radiofrequency signals, a correlation stage (4) and a clock signal generator. The oscillator receives at one input a clock signal with a first frequency (CLK) which clocks the oscillator operations, and a binary word of several bits (Nb) to provide at one output at least an output signal (Mb) with a frequency determined as a function of said binary word and the clock signal. The oscillator includes a first accumulation stage (12) for a first number of most-significant bits (Ob) of the binary word and a second accumulation stage (12) for a second number of least-significant bits (Pb) of said binary word. The first accumulation stage is clocked at the first clock frequency (CLK) to supply the determined frequency output signal (Mb), while the second stage is clocked at a second clock frequency (CLK/N) N times lower than the first clock frequency.

Abstract: The radiofrequency signal receiver (1) includes means (3) for receiving and shaping radiofrequency signals into intermediate signals (IF), a correlation stage (7) which includes several correlation channels (7′) for receiving the intermediate signals (IF), microprocessor means (12) connected to said correlation stage for the transfer of control and/or data signals. The receiver also includes channel selection means, such as a priority decoder (13), connected to all the channels (7′) of the correlation stage (7) and to the microprocessor means (12). These selection means allow the channel with the highest priority among the operating channel or channels which have each transmitted an interruption signal for a data transfer from the selected channel to the microprocessor means (12), to be placed first in a virtual channel, in accordance with a defined order of priority for all the channels.

Abstract: The numerically controlled oscillator (8) is mounted in particular in a radiofrequency signal receiver which further includes means (3) for receiving and shaping the radiofrequency signals, a correlation stage (4) and a clock signal generator. The oscillator receives at one input a clock signal with a first frequency (CLK) which clocks the oscillator operations, and a binary word of several bits (Nb) to provide at one output at least an output signal (Mb) with a frequency determined as a function of said binary word and the clock signal. The oscillator includes a first accumulation stage (12) for a first number of most-significant bits (Ob) of the binary word and a second accumulation stage (12) for a second number of least-significant bits (Pb) of said binary word. The first accumulation stage is clocked at the first clock frequency (CLK) to supply the determined frequency output signal (Mb), while the second stage is clocked at a second clock frequency (CLK/N) N times lower than the first clock frequency.

Abstract: The correlation and demodulation circuit (6) in particular for a pseudo-random code radio-frequency signal receiver (1) includes a correlation stage (7) connected to control means (12) in particular for configuring said correlation stage in normal operating mode or in test mode. In normal operation said stage receives intermediate signals (IF) corresponding to the radio-frequency signals shaped in means (3) for receiving the modulated signals from the receiver. Said intermediate signals are correlated in a correlator control loop (8) of said correlation stage (7) with a replica of the first code supplied by a code generator (25). The code generator (25) is adapted via control means (12) to generate a replica of a pseudo-random code of shorter repetition length than the pseudo-random code of the radio-frequency signals.

Abstract: The low power RF receiver (1) includes an antenna (2), a reception and shaping stage (3) for the radio-frequency signals provided by the antenna, a 12 channel correlation stage (7) receiving intermediate signals (IF) shaped by the reception stage (3), a microprocessor (12) connected to the correlation stage for calculating X, Y and Z position, velocity and time data as a function of data provided by the radio-frequency signals, such as GPS signals, transmitted by the satellites. Each channel includes a correlator (8) associated with a controller (9), which also includes a digital signal processing algorithm to allow all the synchronisation tasks for acquiring and tracking a satellite to be performed autonomously when the channel (7′) is set in operation, and to lock onto the satellite. Buffer registers (11) are placed at the interface between the correlation stage (7) and the microprocessor (12) for the mutual transfer of data.