Abstract: A system, computer program product, and method are presented for executing a validation test on at least a portion of a refactored application. The refactored application is resident within a partitioned computing architecture including a plurality of partitions and communication between the partitions uses one or more boundary methods. The refactored application is at least partially similar to a transformed monolithic application. The method includes automatically generating one or more test sequences for exercising one or more functional behaviors for each boundary method of the one or more boundary methods.

Abstract: Computer interfaces are provided for managing and deploying contextually relevant event canvases based on entity roles. Some systems are configured for identifying events and generating contextually relevant canvases associated with those events, which are contextually based on roles assigned to the events. A master canvas is also provided for facilitating navigation between the various canvases and to assign roles to the canvases, as well as for facilitating management configuration of the canvases. The master canvas includes a tabbed interface that allows navigation, configuration, and insight into the various canvases.

Abstract: Interfaces utilize two types of tiles, including boundary spanning type tiles and boundary non-spanning type tiles. The boundary non-spanning tile each have a boundary non-spanning parameter/property that prevent the tile from overlapping a particular type of display boundary and that is operable for triggering a modification of a layout presentation of the canvas by causing/modifying the one or more tiles in the first set of tiles to be automatically resized and/or repositioned within the canvas layout presentation when it is determined the boundary non-spanning type tile(s) would overlap the particular type of boundary in a current/prior layout. The boundary spanning type tiles omit the boundary non-spanning parameter/property or have it set to an inactive state.

Abstract: Computer interfaces are provided for accessing and displaying content from disparate and remotely connected computer systems and that can be used for facilitating collaboration and visualization of physical and cloud resources for distributed event management. Systems are provided for generating, modifying, deploying, accessing, and otherwise managing the computer interfaces. Templates are used to build canvas interfaces that are contextually relevant for different entities based on the context of associated events and assigned roles of the entities with respect to the different events. The canvas interfaces can be used to access and orchestrate resources associated with the different events.

Abstract: Interactive event creation control consoles are provided to facilitate the creation of events from a plurality of different content sources. In some instances, the event creation control consoles include two different frames, a content source frame for selecting content for corresponding content tiles and an event creation frame for identifying the content tiles to be published in an event canvas associated with a particular event and which is published differently on different end user systems based on the contextual event role of the end user and/or the different end user system configurations.

Abstract: An unobservable cycle for at least one latch in a circuit design is detected. The unobservable cycle indicates that the at least one latch is not observable to downstream logic in the circuit design. A coverage event is generated to identify the unobservable cycle for the at least one latch. The coverage event is tracked to detect a state associated with the unobservable cycle and a state change cycle. The state change cycle is determined based on a simulation technique. A redundant switching of the at least one latch based on the state associated with the unobservable cycle and the state change cycle is determined. Furthermore, manufacturing of a circuit based on the circuit design is at least initiated. The circuit design is modified to prevent the redundant switching of the at least one latch.

Abstract: An unobservable cycle for at least one latch in a circuit design is detected. The unobservable cycle indicates that the at least one latch is not observable to downstream logic in the circuit design. A coverage event is generated to identify the unobservable cycle for the at least one latch. The coverage event is tracked to detect a state associated with the unobservable cycle and a state change cycle. The state change cycle is determined based on a simulation technique. A redundant switching of the at least one latch based on the state associated with the unobservable cycle and the state change cycle is determined. Furthermore, manufacturing of a circuit based on the circuit design is at least initiated. The circuit design is modified to prevent the redundant switching of the at least one latch.

Abstract: Computer interfaces are provided for dynamically binding event data with standard operating procedures. Systems are provided for identifying an event and an event context from received event data streams. Procedures are generated that are related to the context of the event. Content tiles that include event data streams are then dynamically bound to the procedures in a way that allows content tiles to be surfaced or modified when the procedures utilized. Systems are also configured for dynamically updating procedures based on detecting a change in the context of an underlying event.

Abstract: Interfaces utilize two types of tiles, including boundary spanning type tiles and boundary non-spanning type tiles. The boundary non-spanning tile each have a boundary non-spanning parameter/property that prevent the tile from overlapping a particular type of display boundary and that is operable for triggering a modification of a layout presentation of the canvas by causing/modifying the one or more tiles in the first set of tiles to be automatically resized and/or repositioned within the canvas layout presentation when it is determined the boundary non-spanning type tile(s) would overlap the particular type of boundary in a current/prior layout. The boundary spanning type tiles omit the boundary non-spanning parameter/property or have it set to an inactive state.

Abstract: Computer interfaces are provided for managing and deploying contextually relevant event canvases based on entity roles. Some systems are configured for identifying events and generating contextually relevant canvases associated with those events, which are contextually based on roles assigned to the events. A master canvas is also provided for facilitating navigation between the various canvases and to assign roles to the canvases, as well as for facilitating management configuration of the canvases. The master canvas includes a tabbed interface that allows navigation, configuration, and insight into the various canvases.

Abstract: Computer interfaces are provided for accessing and displaying content from disparate and remotely connected computer systems and that can be used for facilitating collaboration and visualization of physical and cloud resources for distributed event management. Systems are provided for generating, modifying, deploying, accessing, and otherwise managing the computer interfaces. Templates are used to build canvas interfaces that are contextually relevant for different entities based on the context of associated events and assigned roles of the entities with respect to the different events. The canvas interfaces can be used to access and orchestrate resources associated with the different events.

Abstract: Interactive event creation control consoles are provided to facilitate the creation of events from a plurality of different content sources. In some instances, the event creation control consoles include two different frames, a content source frame for selecting content for corresponding content tiles and an event creation frame for identifying the content tiles to be published in an event canvas associated with a particular event and which is published differently on different end user systems based on the contextual event role of the end user and/or the different end user system configurations.

Abstract: A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.

Abstract: A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.

Abstract: A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.

Abstract: A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.

Abstract: A method, apparatus and product for detecting corresponding paths in combinationally equivalent circuit designs. The method comprising: obtaining a first circuit design and a second circuit design, the first and second circuit designs have corresponding sets of input and output elements; obtaining a path in the first circuit design, the path commencing in an input element and ending in an output element, wherein the input element and the output element are connected by combinational logic elements; automatically extracting, by a computer, a sensitization function of the path in the first circuit design; and automatically determining, by the computer, one or more paths in the second circuit design which are sensitized by the sensitization function of the path.

Abstract: A method, apparatus and product for detecting corresponding paths in combinationally equivalent circuit designs. The method comprising: obtaining a first circuit design and a second circuit design, the first and second circuit designs have corresponding sets of input and output elements; obtaining a path in the first circuit design, the path commencing in an input element and ending in an output element, wherein the input element and the output element are connected by combinational logic elements; automatically extracting, by a computer, a sensitization function of the path in the first circuit design; and automatically determining, by the computer, one or more paths in the second circuit design which are sensitized by the sensitization function of the path.

Abstract: A circuit design, responsive the input signals, may be obtained and processed. The circuit design may define connections between combinational elements, memory elements, and input signals. Identification of cut-off points may be performed with respect to predetermined combinational logic input signals. The cut-off points may be connections whose values are not dependant on the value of the predetermined combinational logic input signals. An approximated circuit design may be synthesized by relaxing the logic associated with the cut-off points. Based on the approximated circuit design, processing may be performed. In some exemplary embodiments, a clock gating function of a memory element may be determined by approximating the circuit design with respect to the output signal of the memory element. The clock gating function may be determined based on the approximated circuit design and introduced to the circuit design, with or without additional refinement.

Abstract: A method, apparatus and computer program product for automatic parity check identification. The method comprising: automatically identifying a parity signal in a circuit design, wherein the parity signal is defined as a parity function of a set of support signals, wherein the automatic identification comprises: obtaining a candidate parity signal and a corresponding set of candidate support signals; and verifying that a bit flip in exactly one of any of the corresponding candidate set of support signals induces a bit flip on a value of the candidate parity signal; wherein said method further comprises reporting the automatically identified parity signal.