Abstract: A peripheral data storage subsystem is for use with a computer system. The computer system has a host PCI bus and a serial PCI host bus adapter coupled to the host PCI bus. The peripheral data storage subsystem includes a plurality of data storage devices and a data storage device to parallel PCI interface that is coupled to each of the data storage devices, a parallel PCI to serial PCI interface coupled to the data storage device to parallel PCI interface and a serial PCI link interconnect. The serial PCI link-interconnect couples the parallel PCI to serial PCI interface of the peripheral data storage subsystem to the serial PCI host bus adapter of the computer system.

Abstract: A combined computer system and peripheral data storage subsystem include a computer system has a host PCI bus and a parallel PCI to serial PCI bridge coupled to the host PCI bus and a peripheral data storage subsystem having an enclosure having a back-plane with slots for fifteen serial ATA storage devices, fifteen serial ATA data storage devices each of which is inserted into one of the fifteen slots of the back-plane, a first serial ATA to parallel PCI bridge disposed in the enclosure and coupled to each of eight of the fifteen serial ATA storage devices, a second serial ATA to parallel PCI bridge disposed in the enclosure and coupled to each of the remaining seven of the fifteen serial ATA storage devices and a parallel PCI to serial PCI bridge coupled to the first and second serial ATA to PCI parallel bridges, and a serial PCI link interconnect wherein the serial PCI link interconnect couples the parallel PCI to serial PCI bridge of the peripheral data storage subsystem to the serial PCI host bus adapter

Abstract: A peripheral data storage subsystem is for use with a computer system. The computer system has a host PCI bus and a serial PCI host bus adapter coupled to the host PCI bus. The peripheral data storage subsystem includes a plurality of data storage devices and a data storage device to parallel PCI interface that is coupled to each of the data storage devices, a parallel PCI to serial PCI interface coupled to the data storage device to parallel PCI interface and a serial PCI link interconnect. The serial PCI link interconnect couples the parallel PCI to serial PCI interface of the peripheral data storage subsystem to the serial PCI host bus adapter of the computer system.

Abstract: A peripheral data storage subsystem is for use with a computer system. The computer system has a host PCI bus and a serial PCI host bus adapter coupled to the host PCI bus. The peripheral data storage subsystem includes a plurality of data storage devices and a data storage device to parallel PCI interface that is coupled to each of the data storage devices, a parallel PCI to serial PCI interface coupled to the data-storage device to parallel PCI interface and a serial PCI link interconnect. The serial PCI link-interconnect couples the parallel PCI to serial PCI interface of the peripheral data storage subsystem to the serial PCI host bus adapter of the computer system.

Abstract: A casing of a computer peripheral enclosure. The casing has at least one compartment. Each compartment is rectangular and has a cross-sectional area and a depth. Each compartment also has two guide rail guides. A canister for use with a storage device includes a u-shaped tray which is rectangular and has a cross-sectional area and a depth. The canister has two guide rails. The cross-sectional area and the depth of the canister are slightly less than the cross-sectional area and the depth of each compartment. The u-shaped tray also has two side walls and a two return lips so that the u-shaped tray is able to slide freely, but snugly, into the compartment of the casing. Each guide rail is mechanically coupled to one of the side walls of the u-shaped tray walls. The guide rails of each u-shaped tray slides freely, but snugly, into one of the compartments on the guide rail guides thereof.

Abstract: Initial start-up of a polyphase, brushless DC motor (used for a hard disk drive system) is accomplished by sequentially applying current to each of the phases of the motor. When a back EMF zero-crossing is detected in one of the phases of the motor, after an appropriate delay to allow the next phase to come into position, current is applied to that phase. Thus, the position of the rotor is determined from the back EMF zero-crossing of the phase to which power is currently being supplied. A delay proportional to the speed of the motor is used between the detection of a back EMF zero-crossing and the powering of the next phase in sequence.