Abstract: A method includes determining a set of k extreme values of a dataset of elements in a constant time irrespective of the size of the dataset. A method creates a set of k indicators, each indicator associated with one multi-bit binary number in a large dataset of multi-bit binary numbers. The method includes arranging the multi-bit binary numbers such that each bit n of each said multi-bit binary number is located in a different row n of an associative memory array, starting from a row storing a most significant bit (MSB), adding an indicator to the set for each multi-bit binary number having a bit with an extreme value in the row and continuing the adding until said set contains k indicators.

Abstract: A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: An in-memory computing device includes a memory array, a multiple row decoder and a sensing circuit. The memory includes non-destructive memory cells, each of which includes an 8T-SRAM to store a bit of data. Each cell is connected to a read word line and a write word line, both connecting a row of said memory cells, a write bit line and a complementary write bit line, and a read bit line connecting a single column of said memory cells. The multiple row decoder activates at least two read word lines at a same time. The sensing circuit detects a signal on each of the selected read bit lines of multiple selected columns for reading. Each signal is a Boolean function of the stored data in the memory cells in its column activated by the activated read word lines.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability for selected write data in a bit line section to be logically combined (e.g. logically ANDed) with the read result on a read bit line, as if the write data were the read data output of another computational memory cell being read during the read operation. When accumulation logic is implemented in the bit line sections, the implementation and utilization of additional read logic circuitry provides a mechanism for selected write data in a bit line section to be used as the data with which the read result on the read bit line accumulates, before the newly accumulated result is captured and stored in the bit line section's read register.

Abstract: A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.

Abstract: Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array. Additionally disclosed is a method of computing inside a memory array including non-volatile memory cells arranged in rows and columns, the method includes activating at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and writing data associated with the parametric change into the memory array.

Abstract: A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to inhibit writes in selective bit line sections on per-write operation basis to enhance the computational capability of the bl-sects. The read and write data processing apparatus and method also provides a mechanism to inhibit the read bit line pre-charge in selective bit line sections for an extended period of time to save power when pre-charge circuitry is implemented on the read bit line. The read and write data processing apparatus and method also provides a mechanism to inhibit writes to memory cells in selective bl-sects for an extended period of time, to save power.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: A method and a system for selecting items one by one from a set of items in an associative memory array includes determining a density of the set, if the density is sparse, repeatedly performing an extreme item select (EIS) method to select a next one of the elected items from the set and removing the next one from the set to create a next set, and if the density is not sparse, performing a next index select (NIS) method to create a linked list of the elected items and to repeatedly select a next elected item from the set. An associative memory array includes a plurality of associative memory cells arranged in rows and columns where each first cell in a first row and in a first column has access to a content of a second cell in a second row in an adjacent column.

Abstract: A multiple instruction, multiple data memory device includes a memory array with several sections, one or more multiplexers between the sections and a decoder. Each section has memory cells arranged in rows and columns. The cells in a row are connected by a read enabled word line and by a write enabled word line. The decoder includes a decoder memory array which generally simultaneously activates a plurality of read enabled word lines in several sections, a plurality of write enabled word lines in several sections and one or more multiplexers. The decoder memory array includes several bit lines oriented perpendicularly to and connected to the rows of the memory array. A method of activating in-memory computation using several bit lines of a decoder memory array, connected to rows of the memory array to simultaneously activate several read enabled word lines, several write enabled word lines and one or more multiplexers.

Abstract: A computing device includes bit line processors, multiplexers and a decoder. Each bit line processor includes a bit line of memory cells and each cell stores one bit of a data word. A column of bit line processors stores the bits of the data word. Each multiplexer connects a bit line processor in a first row of bit line processors to a bit line processor in a second row of bit line processors. The decoder activates at least two word lines of the bit line processor of the first row and a word line in the bit line processor in the second row and enables a bit line voltage associated with a result of a logical operation performed by the bit line processor in the first row to be written into the cell in the bit line processor in the second row.

Abstract: A method for machine learning includes extracting features from a training set of inputs, wherein each input generates a feature set and each the feature set forms a neural network key. The method includes arranging the keys in an in-memory computational layer such that the distance between any pair of keys corresponding to similar inputs is as close as possible while keys for a pair of dissimilar inputs have differing values as far apart as possible, wherein each of the keys has a fixed size. The method also includes searching through the dataset using an in-memory K-nearest neighbor unit to find K keys similar to a query key, the searching occurring in a constant amount of time as a function of the fixed size and irrespective of a size of the dataset.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: A multiple instruction, multiple data memory device includes a memory array with several sections, one or more multiplexers between the sections and a decoder. Each section has memory cells arranged in rows and columns. The cells in a row are connected by a read enabled word line and by a write enabled word line. The decoder includes a decoder memory array which generally simultaneously activates a plurality of read enabled word lines in several sections, a plurality of write enabled word lines in several sections and one or more multiplexers. The decoder memory array includes several bit lines oriented perpendicularly to and connected to the rows of the memory array. A method of activating in-memory computation using several bit lines of a decoder memory array, connected to rows of the memory array to simultaneously activate several read enabled word lines, several write enabled word lines and one or more multiplexers.

Abstract: A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry. The responder signal circuitry performs a calculation on a row of the memory array and generates a responder signal indicating that there is at least one cell in the row having a predefined value.

Abstract: A method includes determining a set of k extreme values of a dataset of elements in a constant time irrespective of the size of the dataset. A method creates a set of k indicators, each indicator associated with one multi-bit binary number in a large dataset of multi-bit binary numbers. The method includes arranging the multi-bit binary numbers such that each bit n of each said multi-bit binary number is located in a different row n of an associative memory array, starting from a row storing a most significant bit (MSB), adding an indicator to the set for each multi-bit binary number having a bit with an extreme value in the row and continuing the adding until said set contains k indicators.