Abstract: A pharmaceutical compounding system includes a plurality of vials and a receptacle. The system is arranged to remove substances stored within the vials and combine them within the receptacle to form a medication, and each vial is continuously maintained gripped within the system during preparation of the medication.

Abstract: An apparatus for filling a syringe with a verified dose of radiant fluid has a container holder that holds a container of the radiant fluid wherein a syringe oriented at a septum of the container can penetrate the septum. The syringe holder is configured to continuously grip the syringe, to drive the syringe to the container holder and penetrate the septum, to fill the syringe with a dose of the radiant fluid from the container, to drive the syringe to a transfer post, to drive the syringe to a metering zone of a metering station in order to verify that measured radiation is compatible with the dose, and to release the continuous grip.

Abstract: An apparatus for filling a syringe with a verified dose of radiant fluid has a container holder that holds a container of the radiant fluid wherein a syringe oriented at a septum of the container can penetrate the septum. The syringe holder is configured to continuously grip the syringe, to drive the syringe to the container holder and penetrate the septum, to fill the syringe with a dose of the radiant fluid from the container, to drive the syringe to a transfer post, to drive the syringe to a metering zone of a metering station in order to verify that measured radiation is compatible with the dose, and to release the continuous grip.

Abstract: An addressable memory having: a buffer memory adapted for coupling to a bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network, coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. In a preferred embodiment, the buffer memory includes a first-in/first out (FIFO). A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes: a bus; a controller; and, an addressable memory. The controller and addressable memories are interconnected through the bus. The addressable memory includes a master memory unit and a slave memory unit.

Abstract: An addressable memory having: a buffer memory adapted for coupling to a bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network, coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. In a preferred embodiment, the buffer memory includes a first-in/first out (FIFO). A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes: a bus; a controller; and, an addressable memory. The controller and addressable memories are interconnected through the bus. The addressable memory includes a master memory unit and a slave memory unit.

Abstract: An addressable memory having: a buffer memory adapted for coupling to a bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network, coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. In a preferred embodiment, the buffer memory includes a first-in/first out (FIFO). A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes: a bus; a controller; and, an addressable memory. The controller and addressable memories are interconnected through the bus. The addressable memory includes a master memory unit and a slave memory unit.

Abstract: A system and method for reconstructing data, and/or generating a parity bit for use in reconstructing data, in a data storage system having a set of disk drives and an associated redundant disk drive. The system includes a memory having an exclusive OR gate to provide an accumulated exclusive ORing of the data successively coupled thereto. The accumulated exclusive OR result is coupled to the redundant disk drive in generating the parity bit or to a replaced disk drive when reconstructing data. The system includes: a bus; a controller coupled between the bus and the disk drives; an addressable memory coupled to the bus. The memory includes: a write buffer memory having an input coupled to the bus; a read buffer memory having an output coupled to the bus; and, the exclusive OR logic unit having a pair of inputs. One input is coupled to an output of the write buffer memory and another input is coupled to the output of the read buffer memory.

Abstract: In an data storage system having a bank of disk drives an addressable memory has a buffer memory coupled to a bus, a random access memory coupled to the buffer memory, an internal clock, and a logic network. The logic network is coupled to the bus and configured to transfer data among the buffer memory, the random access memory, and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. The addressable memory is included in an interface and further includes a master memory unit and a slave memory unit.

Abstract: A computer/disk storage system interface is provided having disk controller, CPU controller, and cache memory printed circuit boards interconnected through buses provided in a backplane. The backplane has columns of electrical connectors. Each electrical connector has a plurality of rows of pins. One portion of the pins in each row is electrically connected to one bus and the other portion of the pins is electrically connected to the other bus. Each printed circuit board has an electrical connector adapted to connect with the backplane electrical connectors. While the number of pins in the each row of the cache memory printed circuit board electrical connector is the same as the number of pins in each row of the backplane electrical connector, the number of pins in each row of the controller printed circuit board electrical connector is less than the number of pins in the row of pins in the backplane electrical connector.

Abstract: An addressable memory having: a buffer memory adapted for coupling to a bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network, coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. In a preferred embodiment, the buffer memory includes a first-in/first out (FIFO). A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes: a bus; a controller; and, an addressable memory. The controller and addressable memories are interconnected through the bus. The addressable memory includes a master memory unit and a slave memory unit.

Abstract: A computer/disk storage system is provided for enabling data to be transferred between a memory and either one of a pair of buses. The system includes a pair of logic networks. The first logic network is adapted to enable data to be transferred between the memory and a first one of the buses in response to a first bus availability signal. The first logic network also provides a second bus availability signal indicating when the memory is available to transfer data between such memory and the second one of the buses. A second logic network is adapted to enable data to be transferred between the memory and the second one of the buses in response to the second bus availability signal. The second logic network also provides the first bus availability signal indicating when the memory is available to transfer data between such memory and the second one of the buses.

Abstract: Two data communication channels having electrical ground positions that alternate with control and data positions are terminated in a single, dual-channel connector that occupies generally the same interconnection board real estate as is required for a single, prior art, data communication SI connector, such as for a Small Computer System Interface (SCSI) communication channels. A two-channel SCSI connector system and connection method includes providing a two-channel header having two ground buses, to which the alternating electrical ground wires of respective first and second SCSI channels are terminated. Only a few of the pins or positions of the two-channel connector are connected to the two ground buses while the majority of pins or positions are connected to the signal (control, data) wires of the two SCSI channels.

Abstract: A computer/disk storage system enables data to be transferred between a memory and either one of a pair of buses. The system includes a pair of logic networks. The first logic network enables data to be transferred between the memory and a first one of the buses in response to a first bus availability signal. The first logic network also provides a second bus availability signal indicating when the memory is available to transfer data between such memory and the second one of the buses. A second logic network enables data to be transferred between the memory and the second one of the buses in response to the second bus availability signal. The second logic network also provides the first bus availability signal indicating when the memory is available to transfer data between such memory and the second one of the buses. A clock pulse generator has a pair of oscillators for producing clock pulses from one of the pair of oscillators.

Abstract: A data storage system is provided wherein each one of a plurality of disk interfaces is coupled to a corresponding storage disk drive. The disk interfaces in one portion are coupled through a first unidirectional channel to a first disk controller and the disk interfaces in another portion of the disk interfaces are coupled through a second unidirectional channel to a second disk controller. Each disk interface includes a switch adapted to allow data to pass to another disk drive in the channel thereof; and, when the other channel becomes inoperative, coupling the disk drive in the inoperative channel to the operative fiber channel. With such arrangement, a disk drive may be removed without requiring a shut-down of the storage system (i.e., the disk drive may be "hot swapped"). In one embodiment, a pair of the switches is disposed on the common printed circuit board with the disk interface for enabling depopulation, or removal of, disk drives from the storage system.

Abstract: First and second pairs of pins and cooperative first and second pairs of pin receiving apertures are provided at the confronting connector faces of each of one or more data storage device carrier subassemblies and an interconnection board of a storage system card cage subassembly into which each data storage device carrier subassembly is slidably mounted. The first pin/aperture pair engage and cooperate first to prealign, mechanically support and vibrationally damp each data storage device carrier subassembly.

Abstract: In one embodiment of a two-channel SCSI-compatible interconnection system and method, a dielectric material into which SCSI data and control signal carrying wires are embedded frees ground wires in the SCSI cable to carry first and second SCSI channels so that one conventional SCSI cable and cable connector can support two separate SCSI channels without signal ground wires. In another embodiment of a two-channel SCSI compatible interconnection system and method, a high-density, 100 position dual channel SCSI connector having connector positions doubled in number and spaced at halved intervals relative to a conventional SCSI cable connector supports two separate SCSI channels. In this embodiment, a single one hundred (100) wire SCSI cable or two (2) fifty (50) wire SCSI cables may be attached to the high-density dual channel SCSI connector. In all embodiments, the SCSI channel handling capability is effectively doubled over the heretofore known SCSI connectors for a given connector size or footprint.

Abstract: A memory system wherein a plurality of memory banks is provided, each having a plurality of addressable memory units. A driver is coupled to a set of address terminals of a corresponding one of the memory units in each one of the memory banks. Each bit of data is fed to a data terminal of a corresponding one of the memory units in each one of the memory banks. An error detection and correction (EDAC) unit is fed by the data passing to, or from, the memory system. With such an arrangement, a failure of any one of the drivers results in an error in only one bit of the data stored in the incorrectly addressed location, and such single bit error is corrected by the EDAC unit upon its retrieval from the memory system.