Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.

Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a write command from the host that is recognized by the storage system as a read host memory command; in response to receiving the write command, send an identification of a location in the host memory to the host; and receive, from the host, data that is stored in the location in the host memory. Other embodiments are provided.

Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.

Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.

Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.

Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a write command from the host that is recognized by the storage system as a read host memory command; in response to receiving the write command, send an identification of a location in the host memory to the host; and receive, from the host, data that is stored in the location in the host memory. Other embodiments are provided.

Abstract: A method for data protection in a memory system includes receiving, from entity, an address range and a set command, the address range corresponding to at least a portion of a memory partition in the memory system. The method further includes determining whether the entity is an authenticated entity. The method further includes based on the determination of whether the entity is an authenticated entity, setting, using the set command, access characteristics of the portion of the partition corresponding to the address range.

Abstract: Technology is disclosed that provides security for data stored in a non-volatile memory device. The non-volatile memory device may be embedded in a host system. The host system may further have a host controller that is configured to obtain a memory access message from an initiator to access the non-volatile memory. The host controller may be further configured to provide the memory access message to the memory controller. The memory access message may contain an identifier of the initiator, which may be verified by the host controller. The memory controller may be configured to access the identifier of the initiator from the memory access message, and grant or deny non-volatile memory access to the initiator based on whether the initiator has access rights to a region of the non-volatile memory to which the initiator seeks access.

Abstract: A controller receives an indication that a memory management table loaded to a random-access storage device is in a corrupted state. The controller retrieves one or more error recovery parameters of a memory unit stored in metadata of a physical block of a plurality of physical blocks of the non-volatile storage device. The controller examines the one or more error recovery parameters to determine whether the one or more error recovery parameters indicate the memory unit is fresh or stale. The controller updates the memory management table with logical-to-physical translation information of the metadata for the memory unit that is determined to be fresh. The controller writes the updated memory management table to the non-volatile storage device.

Abstract: Technology is disclosed that provides security for data stored in a non-volatile memory device. The non-volatile memory device may be embedded in a host system. The host system may further have a host controller that is configured to obtain a memory access message from an initiator to access the non-volatile memory. The host controller may be further configured to provide the memory access message to the memory controller. The memory access message may contain an identifier of the initiator, which may be verified by the host controller. The memory controller may be configured to access the identifier of the initiator from the memory access message, and grant or deny non-volatile memory access to the initiator based on whether the initiator has access rights to a region of the non-volatile memory to which the initiator seeks access.

Abstract: A controller receives an indication that a memory management table loaded to a random-access storage device is in a corrupted state. The controller retrieves one or more error recovery parameters of a memory unit stored in metadata of a physical block of a plurality of physical blocks of the non-volatile storage device. The controller examines the one or more error recovery parameters to determine whether the one or more error recovery parameters indicate the memory unit is fresh or stale. The controller updates the memory management table with logical-to-physical translation information of the metadata for the memory unit that is determined to be fresh. The controller writes the updated memory management table to the non-volatile storage device.

Abstract: Data transfer between a data storage device and a peripheral device bypasses an application processor that is coupled to the data storage device and to the peripheral device. In one embodiment, the data storage device includes a memory controller configured to receive, from an application processor, a message indicating a set of logical addresses and a data transfer identifier corresponding to the set of logical addresses. The memory controller is responsive to a request for memory access that includes the data transfer identifier and that is received from a peripheral device. The memory controller is configured to respond to the request by performing a memory access operation based on the set of logical addresses.

Abstract: Data transfer between a data storage device and a peripheral device bypasses an application processor that is coupled to the data storage device and to the peripheral device. In one embodiment, the data storage device includes a memory controller configured to receive, from an application processor, a message indicating a set of logical addresses and a data transfer identifier corresponding to the set of logical addresses. The memory controller is responsive to a request for memory access that includes the data transfer identifier and that is received from a peripheral device. The memory controller is configured to respond to the request by performing a memory access operation based on the set of logical addresses.

Abstract: A memory system and method for improving read latency of a high-priority partition are provided. In one embodiment, a memory system receives a command to store data in the memory. The memory system determines if the command specified that the data is to be stored in a standard partition in the memory or in a high-priority partition in the memory. If the command specified that the data is to be stored in a standard partition in the memory, the memory system stores the data using a first write technique. If the command specified that the data is to be stored in a high-priority partition in the memory, the memory system stores the data using a second write technique, wherein the second write technique provides improved read latency of the stored data. Other embodiments are disclosed.

Abstract: Systems and methods disclosed herein receive a network application proxy (NAP)-extended API function call issued by a networking-aware host application. The NAP-extended API function call provides parameter values associated with a host off-loadable packet exchange sequence. Using the parameter values, a NAP module intercepts and responds to one or more incoming network packets associated with the host off-loadable packet exchange sequence while the host processor is in a sleep mode state or is transitioning between sleep mode states.