Abstract: An aspect includes detecting a user gesture at a sender device, the user gesture indicating a direction relative to the sender device. One or more candidate receiver devices in the indicated direction and in a line-of-sight of the sender device are located. The data to be transferred by the sender device and an action to be performed on the data are identified. It is determined whether any of the one or more candidate receiver devices are configured to accept the data and to perform the action. The data is transferred to a selected one of the one or more candidate receiver devices based on determining that the selected candidate receiver device is configured to accept the data and to perform the action.

Abstract: Methods, systems and computer program products for updating a route of a vehicle based on a broadcast emergency signal are provided. Aspects include receiving, by a navigational device associated with the vehicle, the broadcast emergency signal indicating a route of an emergency vehicle and determining, by the navigational device, whether the route of the vehicle associated with the navigational device overlaps with the route of the emergency vehicle. Aspects also include determining a revised route for the vehicle based on a determination that the route of the vehicle associated with the navigational device overlaps with the route of the emergency vehicle.

Abstract: An aspect includes detecting a user gesture at a sender device, the user gesture indicating a direction relative to the sender device. One or more candidate receiver devices in the indicated direction and in a line-of-sight of the sender device are located. The data to be transferred by the sender device and an action to be performed on the data are identified. It is determined whether any of the one or more candidate receiver devices are configured to accept the data and to perform the action. The data is transferred to a selected one of the one or more candidate receiver devices based on determining that the selected candidate receiver device is configured to accept the data and to perform the action.

Abstract: Methods, systems and computer program products for updating a route of a vehicle based on a broadcast emergency signal are provided. Aspects include receiving, by a navigational device associated with the vehicle, the broadcast emergency signal indicating a route of an emergency vehicle and determining, by the navigational device, whether the route of the vehicle associated with the navigational device overlaps with the route of the emergency vehicle. Aspects also include determining a revised route for the vehicle based on a determination that the route of the vehicle associated with the navigational device overlaps with the route of the emergency vehicle.

Abstract: Methods, systems and computer program products for updating a route of a vehicle based on a broadcast emergency signal are provided. Aspects include receiving, by a navigational device associated with the vehicle, the broadcast emergency signal indicating a route of an emergency vehicle and determining, by the navigational device, whether the route of the vehicle associated with the navigational device overlaps with the route of the emergency vehicle. Aspects also include determining a revised route for the vehicle based on a determination that the route of the vehicle associated with the navigational device overlaps with the route of the emergency vehicle.

Abstract: A system and method for providing a configurable command sequence for a memory interface device (MID). The system includes a MID intended for use in a cascade interconnect system and in communication with one or more memory devices. The MID includes a first connection to a high speed bus operating at a first data rate, a second connection to the high speed bus, an alternate communication means and logic. The first connection to the high speed bus includes receiver circuitry operating at the first data rate. The alternate communication means operates at a second data rate that is slower than the first data rate. The logic facilitates receiving commands via the first connection from the high speed bus operating at the first data rate and using a first command sequence. The logic also facilitates receiving the commands via the alternate communication means using a second command sequence which differs from the first command sequence in the speed in which the commands are transferred.

Abstract: A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.

Abstract: A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.

Abstract: A system and method for providing a configurable command sequence for a memory interface device (MID). The system includes a MID intended for use in a cascade interconnect system and in communication with one or more memory devices. The MID includes a first connection to a high speed bus operating at a first data rate, a second connection to the high speed bus, an alternate communication means and logic. The first connection to the high speed bus includes receiver circuitry operating at the first data rate. The alternate communication means operates at a second data rate that is slower than the first data rate. The logic facilitates receiving commands via the first connection from the high speed bus operating at the first data rate and using a first command sequence. The logic also facilitates receiving the commands via the alternate communication means using a second command sequence which differs from the first command sequence in the speed in which the commands are transferred.

Abstract: A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.

Abstract: A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.