Patents by Inventor Elias Dagher
Elias Dagher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250096810Abstract: A training signal generator for forming an input signal for an ADC-under-test includes a one-bit DAC and an analog low-pass filter. The one-bit DAC converts a binary sequence into a DAC output signal that is then filtered by the analog low-pass filter to form an ADC input signal. The ADC-under-test converts the ADC input signal into an ADC output signal. A digital low-pass filter converts the binary sequence into a plurality of samples. A digital signal processing system processes the plurality of samples and the ADC output signal to form an estimate of the ADC input signal. An ADC linearizer may then be trained to characterize a non-linear impairment of the ADC-under-test responsive to a comparison of the estimate of the ADC input signal and the ADC output signal.Type: ApplicationFiled: September 19, 2023Publication date: March 20, 2025Inventors: Igor GUTMAN, Elias DAGHER, Hua WANG, Behnam SEDIGHI, Seyed Arash MIRHAJ, Tao LUO
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Publication number: 20240305296Abstract: A system includes a switch transistor, and a bootstrap circuit having an input and an output, wherein the output of the bootstrap circuit is coupled to a gate of the switch transistor. The system also includes a first buffer having an input and an output, wherein the output of the first buffer is coupled to a terminal of the switch transistor. The system further includes a second buffer having an input and an output, wherein the input of the second buffer is coupled to the input of the first buffer, and the output of the second buffer is coupled to the input of the bootstrap circuit.Type: ApplicationFiled: March 9, 2023Publication date: September 12, 2024Inventors: Lei SUN, Elias DAGHER, Dinesh Jagannath ALLADI
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Patent number: 11962317Abstract: Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.Type: GrantFiled: May 31, 2022Date of Patent: April 16, 2024Assignee: QUALCOMM IncorporatedInventors: Behnam Sedighi, Shi Bu, Elias Dagher, Dinesh Jagannath Alladi
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Publication number: 20240056043Abstract: An apparatus, including a positive input for an input differential signal; a negative input for the input differential signal; a positive output for an output differential signal; a negative output for the output differential signal; a first capacitor including a first terminal coupled to the positive output; a second capacitor including a first terminal coupled to the negative output; and a switching network configured to: couple a second terminal of the first capacitor to the negative input or a positive node based on a mode signal; and couple a second terminal of the second capacitor to the positive input or a negative node based on the mode signal.Type: ApplicationFiled: August 12, 2022Publication date: February 15, 2024Inventors: Rahul SINGH, Mehran BAKHSHIANI, Timothy Donald GATHMAN, Yuhua GUO, Elias DAGHER
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Patent number: 11901909Abstract: Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.Type: GrantFiled: May 20, 2022Date of Patent: February 13, 2024Assignee: QUALCOMM IncorporatedInventors: Igor Gutman, Behnam Sedighi, Tao Luo, Elias Dagher, Jeremy Darren Dunworth
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Patent number: 11870404Abstract: An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain-stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.Type: GrantFiled: May 13, 2021Date of Patent: January 9, 2024Assignee: QUALCOMM IncorporatedInventors: Kentaro Yamamoto, Aram Akhavan, Ganesh Kiran, Lei Sun, Elias Dagher, Dinesh Jagannath Alladi
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Publication number: 20230387929Abstract: Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.Type: ApplicationFiled: May 31, 2022Publication date: November 30, 2023Inventors: Behnam SEDIGHI, Shi BU, Elias DAGHER, Dinesh Jagannath ALLADI
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Publication number: 20230378970Abstract: Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.Type: ApplicationFiled: May 20, 2022Publication date: November 23, 2023Inventors: Igor GUTMAN, Behnam SEDIGHI, Tao LUO, Elias DAGHER, Jeremy Darren DUNWORTH
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Patent number: 11770129Abstract: An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.Type: GrantFiled: September 24, 2021Date of Patent: September 26, 2023Assignee: QUALCOMM IncorporatedInventors: Seyed Arash Mirhaj, Lei Sun, Yuhua Guo, Elias Dagher, Aram Akhavan, Yan Wang, Dinesh Jagannath Alladi
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Publication number: 20230100825Abstract: An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Seyed Arash Mirhaj, Lei Sun, Yuhua Guo, Elias Dagher, Aram Akhavan, Yan Wang, Dinesh Jagannath Alladi
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Patent number: 11569832Abstract: An apparatus is disclosed for analog-to-digital conversion. In an example aspect, the apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference-crossing detector having an input and an output. The ADC also includes a ramp generator coupled between the output of the reference-crossing detector and the input of the reference-crossing detector. The ADC further includes a voltage shifter coupled between the output of the reference-crossing detector and the input of the reference-crossing detector.Type: GrantFiled: July 26, 2021Date of Patent: January 31, 2023Assignee: QUALCOMM IncorporatedInventors: Aram Akhavan, Seyed Arash Mirhaj, Lei Sun, Elias Dagher
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Publication number: 20230024282Abstract: An apparatus is disclosed for analog-to-digital conversion. In an example aspect, the apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference-crossing detector having an input and an output. The ADC also includes a ramp generator coupled between the output of the reference-crossing detector and the input of the reference-crossing detector. The ADC further includes a voltage shifter coupled between the output of the reference-crossing detector and the input of the reference-crossing detector.Type: ApplicationFiled: July 26, 2021Publication date: January 26, 2023Inventors: Aram Akhavan, Seyed Arash Mirhaj, Lei Sun, Elias Dagher
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Publication number: 20220368299Abstract: An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain- stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Inventors: Kentaro Yamamoto, Aram Akhavan, Ganesh Kiran, Lei Sun, Elias Dagher, Dinesh Jagannath Alladi
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Patent number: 10651864Abstract: A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.Type: GrantFiled: April 25, 2018Date of Patent: May 12, 2020Assignee: QUALCOMM IncorporatedInventors: Timothy Donald Gathman, Yuhua Guo, Lai Kan Leung, Elias Dagher, Dinesh Jagannath Alladi
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Publication number: 20190334539Abstract: A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.Type: ApplicationFiled: April 25, 2018Publication date: October 31, 2019Inventors: Timothy Donald GATHMAN, Yuhua GUO, Lai Kan LEUNG, Elias DAGHER, Dinesh Jagannath ALLADI
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Patent number: 10312927Abstract: Certain aspects of the present disclosure provide methods and apparatus for calibrating time-interleaved analog-to-digital converter (ADC) circuits and generating a suitable signal for such calibration. Certain aspects provide a signal generator for calibrating a time-interleaved ADC circuit having a plurality of channels. The signal generator generally includes a pattern generator configured to receive a periodic signal and to output a bitstream based on the periodic signal and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream. The bitstream has a bit pattern with a total number of bits that shares no common factor with a number of the channels and includes a relatively lower frequency component combined with a relatively higher frequency component.Type: GrantFiled: March 26, 2018Date of Patent: June 4, 2019Assignee: QUALCOMM IncorporatedInventors: Seyed Arash Mirhaj, Elias Dagher, Yongjian Tang, Dinesh Alladi, Masoud Ensafdaran, Lei Sun, Anand Meruva, Yuhua Guo, Balasubramanian Sivakumar
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Patent number: 10277241Abstract: A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC.Type: GrantFiled: April 24, 2018Date of Patent: April 30, 2019Assignee: QUALCOMM IncorporatedInventors: Omid Rajaee, Elias Dagher, Yan Wang, Dinesh Jagannath Alladi
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Patent number: 10243578Abstract: Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.Type: GrantFiled: February 23, 2017Date of Patent: March 26, 2019Assignee: QUALCOMM IncorporatedInventors: Elias Dagher, Yan Wang, Mohammad Meysam Zargham, Dinesh Jagannath Alladi
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Publication number: 20180241409Abstract: Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.Type: ApplicationFiled: February 23, 2017Publication date: August 23, 2018Inventors: Elias DAGHER, Yan WANG, Mohammad Meysam ZARGHAM, Dinesh Jagannath ALLADI
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Publication number: 20180175867Abstract: A method for correcting deterministic jitter in an all-digital phase-locked loop (ADPLL) is described. The method includes determining an offset to an input frequency of the ADPLL that causes an oscillator tuning word (OTW) provided to a digitally-controlled oscillator (DCO) quantizer to fall between two DCO codes. The method also includes applying the offset to the input frequency of the ADPLL to force the DCO quantizer to have gain.Type: ApplicationFiled: December 16, 2016Publication date: June 21, 2018Inventors: Emanuele Lopelli, Charles Wang, Elias Dagher