Abstract: An improved complex-IF digital receiver has various improvements. The improved complex-IF digital receiver, for single or dual band applications, preferably synchronizes all of the signals to each other, which may be an integer multiple of each other. For example, the decimation filter, delta-sigma modulator, sensitivity DAC, and other circuits in the receiver can be synchronized. The delta-sigma modulator preferably includes a comparator whose input is coupled to a sensitivity DAC or synchronous dithering circuit. Ideally, the sensitivity DAC forces the comparator to trigger at every clock cycle and reduces the effect of hysteresis and offset at the input of the comparator. The receiver includes a translation circuit that translates an intermediate frequency signal to baseband, where the translation circuit preferably operates a translation ratio that is a multiple of 4.

Abstract: A sigma-delta analog-to-digital converter (10) having DEM (14) facilitated data weighted averaging to select specific unit elements of a negative feedback loop digital-to-analog converter (15), which DEM (14) is comprised substantially of transmission gates that contribute little to propagation delay. As a result, the feedback signal provided by the feedback loop is not more than one clock cycle behind the present coded output of the ADC (10) itself. As a result, higher resolution converters can be realized. The DEM (14) utilizes a repeating sequence to select specific unit elements. In some embodiments the direction of sequence usage is reversed in various ways to aid in reducing harmonic distortion.

Abstract: A sigma-delta analog-to-digital converter (10) having DEM (14) facilitated data weighted averaging to select specific unit elements of a negative feedback loop digital-to-analog converter (15), which DEM (14) is comprised substantially of transmission gates that contribute little to propagation delay. As a result, the feedback signal provided by the feedback loop is not more than one clock cycle behind the present coded output of the ADC (10) itself. As a result, higher resolution converters can be realized. The DEM (14) utilizes a repeating sequence to select specific unit elements. In some embodiments the direction of sequence usage is reversed in various ways to aid in reducing harmonic distortion.