Patents by Inventor Elias Kougianos

Elias Kougianos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153306
    Abstract: A method of identifying synthetic media can include identifying a facial image in video or images, extracting a first set of features from the facial image, extracting a second set of features from the facial image, wherein the first set of features are different than the second set of features, inputting the first set of features into a first prediction model, generating a first output indicative of a nature of the facial image, inputting the second set of features into a second prediction model, generating a second output indicative of the nature of the facial image, and determining the nature of the facial image using the first output and the second output.
    Type: Application
    Filed: October 11, 2023
    Publication date: May 9, 2024
    Inventors: Saraju P. MOHANTY, Elias KOUGIANOS, Alakananda MITRA
  • Publication number: 20230294514
    Abstract: A system for determining a blood alcohol concentration of an individual includes one or more sensors configured to measure a physiological parameter of an individual, and an analysis unit, and a method for monitoring a state of a driver related thereto. A system for determining a blood alcohol concentration of an individual can include one or more sensors, and an analysis unit configured to receive one or more outputs of the one or more sensors. The one or more sensors are configured to measure a physiological parameter of an individual, and the analysis unit is configured to determine a mental state or a physical state of the individual based on the one or more outputs of the one or more sensors.
    Type: Application
    Filed: March 17, 2023
    Publication date: September 21, 2023
    Inventors: Saraju P. MOHANTY, Elias KOUGIANOS, Laavanya RACHAKONDA
  • Publication number: 20220167916
    Abstract: A wearable device including multiple sensors, a memory, a processor coupled to the memory and the multiple processors, and executable code stored in the memory. When executed by the processor, the executable code causes the processor to receive data from at least some of the multiple sensors, the data indicating physical activity of a wearer of the wearable device, food consumption of the wearer, and sleeping habits of the wearer and determine an estimated stress level of the wearer based on the physical activity of the wearer, the food consumption of the wearer, and the sleeping habits of the wearer.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 2, 2022
    Inventors: Saraju P. MOHANTY, Elias KOUGIANOS, Laavanya RACHAKONDA
  • Patent number: 9053276
    Abstract: A method for designing complex, mixed signal circuits, comprising generating electronic data defining a baseline schematic design. Generating a parameterized parasitic-aware netlist using the baseline schematic design. Performing design and process parameter statistical optimization using the parameterized parasitic-aware netlist and mixed signal component specifications. Determining whether one or more predetermined design specifications are satisfied. Optimizing the parameterized parasitic-aware netlist if it is determined that the one more predetermined design specifications are not satisfied. Generating electronic data defining a schematic-optimal layout design if it is determined that the one or more predetermined design specifications are satisfied.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: June 9, 2015
    Assignee: University of North Texas
    Inventors: Saraju P. Mohanty, Elias Kougianos
  • Patent number: 9026964
    Abstract: A method for modeling a circuit comprising storing a plurality of design variable ranges for a circuit component in a non-transient electronic data memory. Performing transistor-level simulations at a plurality of sample points for the circuit component to generate a plurality of design variable samples for the circuit component. Storing a neural network architecture in the non-transient electronic data memory that models the plurality of design variable samples for the circuit component. Storing a performance metric metamodel and a circuit parameter metamodel generated using Verilog-AMS.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: May 5, 2015
    Assignee: University of North Texas
    Inventors: Saraju P. Mohanty, Elias Kougianos, Geng Zheng
  • Publication number: 20140282314
    Abstract: A method for modeling a circuit comprising storing a plurality of design variable ranges for a circuit component in a non-transient electronic data memory. Performing transistor-level simulations at a plurality of sample points for the circuit component to generate a plurality of design variable samples for the circuit component. Storing a neural network architecture in the non-transient electronic data memory that models the plurality of design variable samples for the circuit component. Storing a performance metric metamodel and a circuit parameter metamodel generated using Verilog-AMS.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: University of North Texas
    Inventors: Saraju P. Mohanty, Elias Kougianos, Geng Zheng
  • Publication number: 20140173537
    Abstract: A method for designing complex, mixed signal circuits, comprising generating electronic data defining a baseline schematic design. Generating a parameterized parasitic-aware netlist using the baseline schematic design. Performing design and process parameter statistical optimization using the parameterized parasitic-aware netlist and mixed signal component specifications. Determining whether one or more predetermined design specifications are satisfied. Optimizing the parameterized parasitic-aware netlist if it is determined that the one more predetermined design specifications are not satisfied. Generating electronic data defining a schematic-optimal layout design if it is determined that the one or more predetermined design specifications are satisfied.
    Type: Application
    Filed: June 27, 2013
    Publication date: June 19, 2014
    Applicant: University of North Texas
    Inventors: Saraju P. Mohanty, Elias Kougianos