Abstract: A method of operating a memory system to compress data efficiently is described. The user data and the associated metadata are separated so that user data having repeating data patterns of greater length than a single user data structure may be assembled for storage. The user metadata and the repeating pattern metadata are stored in non-volatile memory such that the repeating pattern metadata can be used to reconstruct the repeating pattern of individual user data blocks. The reconstructed user data blocks are combined with user metadata, if any, and returned to the user in response to a read request.

Abstract: A value representative of a processor's speculative branch prediction efficiency is determined and the speculative branch prediction depth is adjusted accordingly. The processor's speculative branch prediction efficiency may be represented by the average number of clocks per instruction (CPI), whereby an increase in the average CPI indicates that the processor is becoming less efficient due to incorrectly predicted speculative branch predictions and, conversely, a decrease indicates that the processor has a higher ratio of properly predicted speculative branch predictions.

Abstract: Double data rate (DDR) synchronous dynamic random access memory (SDRAM) data is sampled into a synchronization circuit on both rising and falling edges of a data strobe (DQS) signal, into separate latches. A delay calculation and timing synchronization unit determines the location of the data strobe signal relative to rising/falling edges of an internal clock, then decides which sample to transfer into the internal data path and whether to use the rising or falling internal clock edge. Every DDR-SDRAM read transaction is thus automatically synchronized without the need for predetermined delay(s), allowing a wide range of operating frequencies and frequency variations to be accommodated.

Abstract: A value representative of a processor's speculative branch prediction efficiency is determined and the speculative branch prediction depth is adjusted accordingly. The processor's speculative branch prediction efficiency may be represented by the average number of clocks per instruction (CPI), whereby an increase in the average CPI indicates that the processor is becoming less efficient due to incorrectly predicted speculative branch predictions and, conversely, a decrease indicates that the processor has a higher ratio of properly predicted speculative branch predictions.

Abstract: An apparatus and method is disclosed for avoiding metastability problems during a data transfer between a first circuit operating at first clock frequency and a second circuit operating at a second clock frequency. The first circuit sends an asynchronous control signal to the second circuit. The second circuit samples the asynchronous control signal at least two times and uses at least two samples of the asynchronous control signal to synchronize communication between the first and second circuits. The data is transferred between the first and second circuits when the circuits are synchronized. The second circuit indicates to the first circuit when the data transfer has been completed.

Abstract: An apparatus and method is disclosed for providing a smooth transition between a first clock signal at a first frequency and a second clock signal at a lower second frequency. A pulse is generated that indicates whether the logic levels of the first and the second clock signals are similar or are different. The rising/falling edges of the pulse are synchronized with the rising/falling edges of the first clock signal. When a change in a logic level of a command signal for switching between the clock signals is detected, a first time period is identified in which the logic levels of the first and the second clock signals are different. The transition between the first clock signal and the second clock signal is allowed immediately after the first time period has ended.