Abstract: A method is provided for semiconductor manufacture wherein a via is defined and etched through an insulative layer of the device to an underlying conductive region and metal fillets are formed in the corner regions of the via. A conformal metal layer is then deposited onto the device and etched until all metal is removed from the insulative layer surface. Finally, a second metal interconnect layer is deposited onto the device and the desired interconnect pattern is defined. The fillets displace the metal subsequently deposited on the via side surface laterally toward the center of the via, thereby preventing severe self-shadowing problems and improving step coverage of metal into the via.

Abstract: Cathode migration is reduced by increasing the width of the cathode at its leading edge compared to the width of the anode at its leading edge. Electromigration to a specific degree may be measured by placing an additional conductor connected to the anode portion of the base conductor and separated from the anode by the base conductor. A rapid change in resistance can be sensed as the anode electrically migrates past the additional conductor.