Abstract: A system includes a first device comprising a first clock generating circuit and a transmitter circuit, and a plurality of second devices, each comprising a respective receiver circuit and a respective second clock generating circuit. The first clock generating circuit may be configured to generate a first clock signal, which may provide internal clocking for the first device. The transmitter circuit may be configured to generate a synchronization signal in response to the first clock signal and wirelessly transmit a broadcast signal communicating only the synchronization signal. The respective receiver circuit may be configured to receive the broadcast signal and present a recovered synchronization signal to the respective second clock generating circuit.

Abstract: A system includes a first device comprising a first clock generating circuit and a transmitter circuit, and a plurality of second devices, each comprising a respective receiver circuit and a respective second clock generating circuit. The first clock generating circuit may be configured to generate a first clock signal, which may provide internal clocking for the first device. The transmitter circuit may be configured to generate a synchronization signal in response to the first clock signal and wirelessly transmit a broadcast signal communicating only the synchronization signal. The respective receiver circuit may be configured to receive the broadcast signal and present a recovered synchronization signal to the respective second clock generating circuit.

Abstract: An apparatus includes a first independently clocked device and one or more second independently clocked devices. The first independently clocked device may comprise a clock generator. The clock generator may be configured to generate a clock signal. The first independently clocked device may be configured to wirelessly broadcast a synchronization signal based on the clock signal. The one or more second independently clocked devices may each comprise respective clock generators. The one or more second independently clocked devices may (a) be configured to receive the synchronization signal from the first independently clocked device and (b) synchronize the respective clock generators to the clock signal of the first independently clocked device in response to the synchronization signal.

Abstract: An apparatus includes a first independently clocked device and one or more second independently clocked devices. The first independently clocked device may comprise a clock generator. The clock generator may be configured to generate a clock signal. The first independently clocked device may be configured to wirelessly broadcast a synchronization signal based on the clock signal. The one or more second independently clocked devices may each comprise respective clock generators. The one or more second independently clocked devices may (a) be configured to receive the synchronization signal from the first independently clocked device and (b) synchronize the respective clock generators to the clock signal of the first independently clocked device in response to the synchronization signal.

Abstract: A system, method, and computer program product for pricing options which involve more than one underlying asset. The method employs a lattice approach by extending current trinomial techniques to higher dimensions, while achieving a maximum economy of nodes. Such economy produces computational advantages in terms of faster execution speed and the utilization of less memory resources. The method valuates options under a general form (i.e., Brownian motion) where parameters may depend on time and price, and accounts for drift and volatility parameters.

Abstract: An activity sensor monitors a microprocessor based system for a change in a logic state. In response to the change, the activity sensor provides a reset timer pulse to a delay timer circuit. The delay timer is a counter that stores a signal representation of the number of timing pulses provided by a timing clock. In response to the timer reset signal, the delay timer is reset. When the timer reset pulse is not provided for a predetermined interval, the delay timer generates a timeout pulse that causes a reduction in the frequency of a system clock.

Abstract: An improved clock synthesizer system and method therefor is described which uses a plurality of dual function pins to apply a frequency selection code while in a first operating mode and to transmit buffered clock signal while in a second operating mode to accomplish required system functions with a reduced overall pin count.