Abstract: A frequency synthesizer comprises a single phase-locked loop controlled by a reference clock formed by a voltage-controlled oscillator, a programmable divider with variable division rank M, a phase detector, and a loop filter. It also comprises a predetermined number n of fractional division structures, each implementing a frequency step Pi×FreF lower than the reference frequency Fref.

Abstract: A frequency synthesizer with very short acquisition times. With a single loop there is associated a direct digital synthesizer whose signal is injected into the loop by means of a mixer. The adjustment of the loop is done on Np.Fr and the adjustment of the digital synthesis is done on (Ns+)Fr with Np, Ns, K and M as integers, Np being greater than Ns, 0.ltoreq.K<M, M as a fixed value and where Fr is a reference frequency. The mixture makes it possible to obtain, as a synthesis frequency, (Ns+Np+)Fr. The acquisition time of the digital synthesis is negligible and that of the loop is greatly reduced since it synthesizes steps that are multiples of Fr and not of as with a standard single loop.