Abstract: A novel high-speed phase splitter circuit (100) and method of operation are disclosed. This high-speed phase splitter (100) creates a differential rail-to-rail output signal from a single ended input signal, with an inherent low skew and symmetrical output. The circuit (100) uses a phase splitting input stage (110, 130) followed by several amplification stages (150, 170) that are symmetrical and balanced in nature.

Abstract: A novel high-speed phase splitter circuit (100) and method of operation are disclosed. This high-speed phase splitter (100) creates a differential rail-to-rail output signal from a single ended input signal, with an inherent low skew and symmetrical output. The circuit (100) uses a phase splitting input stage (110, 130) followed by several amplification stages (150, 170) that are symmetrical and balanced in nature.

Abstract: A novel high speed, >1 GHz or 2 Gbits/s, low voltage differential signal (LVDS) driver is disclosed. The LVDS design achieves low power consumption while providing LVDS compliant impedance termination to power supply and ground. An output stage of the LVDS is implemented using a Nmos and a Pmos follower in a push pull configuration. This new design relies first on a follower type of an output stage, which provides the inherent impedance termination, second on an AC, capacitive, coupling and DC restoration to drive output stage gates, and on a low power dummy bias generator that supplies DC restoration voltages. As the supply voltage is lower the thick oxide devices performance suffer, therefore for this new design is mainly implemented with thin oxide devices.

Abstract: A novel high-speed differential receiver is disclosed that provides a new method and apparatus receiving and amplifying a small differential voltage with a rail-to-rail common mode voltage. The receiver output signals are differential signals with low skew and high symmetry. This high-speed differential receiver is based on a common mode voltage normalization, which is based on a differential phase splitting methodology, before the resulting signal is recombined, normalized and amplified. The method involves using a differential signal splitting followed by a common mode voltage normalization stage, then a controlled gain transimpedance amplification, and then amplification using one or two rail to rail amplification stages that are symmetrical and balanced in nature.

Abstract: A novel high-speed differential receiver (100) is disclosed that provides a new method and apparatus receiving and amplifying a small differential voltage with a rail-to-rail common mode voltage. The receiver output signals are differential signals with low skew and high symmetry. This high-speed differential receiver (100) is based on a common mode voltage normalization, which is based on a differential phase splitting methodology, before the resulting signal is recombined, normalized and amplified. The method involves using a differential signal splitting stage (110) followed by a common mode voltage normalization stage (130), then a controlled gain transimpedance amplification stage (150), and then amplification using one or two rail to rail amplification stages (170) that are symmetrical and balanced in nature.

Abstract: An AC electrically coupled FET device (301) is disclosed with a coupling capacitor (302) disposed for receiving a digital input signal having transitions and for AC coupling this input signal to the gate terminal of the FET device (301). A reference bias circuit (306) is provided for providing a first bias voltage (403b) that is above a threshold voltage of the FET device (301) and a second bias voltage (403a), where the first and second bias voltage (403b, 403a) are higher than rail to rail supply voltages. Switching circuitry (304, 305) is electrically coupled with the gate terminal of the FET device (301) for one of coupling of the first bias voltage (403b) and uncoupling of the second bias voltage (403a) and coupling of the second bias voltage (403a) and uncoupling of the first bias voltage (403b) in response to the transitions in the digital input signal.

Abstract: A digital positioning system for a joystick. The system uses a potentiometer having one input coupled to a constant supply voltage and a second input coupled to a joystick game port for generating a variable resistance representative of a current position of the joystick. A constant current source is coupled to the joystick game port for generating a current for converting the variable resistance representative of the current position of the joystick to a voltage level representative of the current position of the joystick. An analog-to-digital (A/D) converter circuit is coupled to the joystick game port and is used to convert the voltage level representative of the current position of the joystick to a digital representation of the current position of the joystick.