Abstract: A non intrusive isolation testing method for each of the positive and negative input (in+ & in−) to each comparator in the array is provided. Isolation does not affect the read capability of the comparator and therefore characterization of the comparator is accomplished by using the normal read circuits of the one time programmable (OTP) array. The isolation method relies on gating the control signals by using test signals; as a result inputs to a comparator are not affected electrically. Each input has four possible control signals and therefore needs four gating test signal drivers and so a total of 16 input combinations are available to each comparator.

Abstract: In a method of measuring fuse resistance in a fuse array, the P-MOS switches used for row address are replaced by a pass-gate device comprising an N-MOS in parallel with a P-MOS, with a close to zero voltage drop. By this means a reduced power source current is applied across the fuse. The voltage drop is measured and the resistance obtained. Thus non-destructive testing is carried out as compared to destructive testing with the prior art method.

Abstract: A non intrusive isolation testing method for each of the positive and negative input (in+ & in−) to each comparator in the array is provided. Isolation does not affect the read capability of the comparator and therefore characterization of the comparator is accomplished by using the normal read circuits of the one time programmable (OTP) array. The isolation method relies on gating the control signals by using test signals; as a result inputs to a comparator are not affected electrically. Each input has four possible control signals and therefore needs four gating test signal drivers and so a total of 16 input combinations are available to each comparator.

Abstract: In a method of measuring fuse resistance in a fuse array, the P-MOS switches used for row address are replaced by a pass-gate device comprising an N-MOS in parallel with a P-MOS, with a close to zero voltage drop. By this means a reduced power source current is applied across the fuse. The voltage drop is measured and the resistance obtained. Thus non-destructive testing is carried out as compared to destructive testing with the prior art method.

Abstract: A secure one-time programmable (OTP) salicided poly fuse array (2×8) cells with a power-on or on-reset hardware security feature is proposed. The secure OTP which is based on a primitive building cell that includes a salicided poly fuse and a MOS switch, utilize the same building block of the un-secure larger OTP array. This includes an enhanced multistage track & latch sense amp, or comparator, primitive memory cells, decoders for write and read mechanism, and a similar control block.

Abstract: Comparators, memory devices, comparison methods and memory reading methods are provided. One aspect provides a comparator including an input stage having a data input adapted to receive a data voltage signal, a reference input adapted to receive a reference voltage signal, and a plurality of current sources individually coupled with one of the data input and the reference input and individually configured to convert one of the data voltage signal and the reference voltage signal to a differential current signal and to output the differential current signal; and a comparator stage including a plurality of inputs configured to receive the differential current signals from the input stage and the comparator stage being configured to compare the differential current signals and to output an output signal indicative of a comparison of the differential current signals.

Abstract: Comparators, memory devices, comparison methods and memory reading methods are provided. One aspect provides a comparator including an input stage having a data input adapted to receive a data voltage signal, a reference input adapted to receive a reference voltage signal, and a plurality of current sources individually coupled with one of the data input and the reference input and individually configured to convert one of the data voltage signal and the reference voltage signal to a differential current signal and to output the differential current signal; and a comparator stage including a plurality of inputs configured to receive the differential current signals from the input stage and the comparator stage being configured to compare the differential current signals and to output an output signal indicative of a comparison of the differential current signals.

Abstract: An integrated circuit driver drives a differential signal over a communication cable, such as a twisted-pair cable. The integrated circuit driver includes a differential pre-driver that receives an input signal having an about 50% duty cycle and produces an amplified differential signal that swings between a power rail level and a ground level. A signal conditioner circuit receives the amplified differential signal and outputs a conditioned differential signal. The conditioned differential signal swings between the power rail level and an intermediate power level. The integrated circuit driver further includes an output driver that receives the conditioned differential signal that swings between the power rail level and the intermediate power level. The output driver produces a differential output signal that is communicated to the communication cable. The differential output signal has an about zero signal crossing and maintains the about fifty percent duty cycle.

Abstract: An improved output driver that minimizes source point reflections when driving a signal on a transmission line by generating a constant source impedance. The improved output driver uses a transistor switching circuit for generating a nearly constant channel impedance when transistor switching circuit is enabled and is not operating in a saturation mode. A switched diode circuit is coupled in parallel to the transistor switching circuit for generating a nearly constant source impedance when a sufficient voltage to bias the switch diode circuit is applied. Control circuitry is coupled to both the transistor switching circuit and to the switched diode circuit for enabling and disabling the transistor switching circuit and the switched diode circuit. By alternatively enabling and disabling the transistor switching circuit and the switched diode circuit the control circuit is able to generate a constant source impedance.

Abstract: There is provided herein a joystick interface which includes circuitry to detect when the joystick output signal has been at a steady-state level for a predetermined period of time and upon detection of that condition, the circuitry powers down at least some of the circuitry associated with providing the digital signal representation to the computer. In one particular embodiment of the invention, analog circuitry including a slope detector, makes use of two non-overlapping clocks to sample data and provide it to a comparator. The comparator is used to determine if there has been any change between consecutive or sequential samples, representative of joystick shaft movement. After a predetermined number of comparisons showing no change in either a neutral joystick position or a non-neutral joystick position, the digital circuitry is powered-down to a reduced power operating mode.

Abstract: A comparator used in an enhanced N-WELL pad voltage tracking circuit for high (5 Volts) voltage-tolerant buffers is designed to eliminate current leakage when the input/output is tristated and is being driven externally by a weak voltage source. This is accomplished by comparing the pad voltage supplied from the external source to a reference voltage that is a predetermined amount (VTP) less than the low internal voltage source (VDD). Thus, switchover for tracking of the N-WELL voltage tracks very closely the voltage VDD, reducing the differential voltage between the N-WELL and the pad on the pull-up driver for the system, thereby keeping the driver off and eliminating leakage current. The reference voltage is generated either by a diode voltage drop or by a weak source follower.