Abstract: New synthetic expression cassettes comprising a minimal promoter and a cell-specific enhancer for expression of a nucleic acid of interest in one or more specific cell subtypes are disclosed. Vectors and host cells comprising such synthetic expression cassettes are also disclosed. The application also discloses methods for expressing a nucleic acid of interest, such as a nucleic acid encoding a chimeric antigen receptor (CAR), in a cell and for treating diseases or conditions such as cancers and genetic diseases using the synthetic expression cassettes, vectors and cells.

Abstract: A method for developing an integrated circuit chip design includes the steps of developing an architecture specification defining the functions of the chip, developing a microarchitecture specification based on the architecture specification, developing a functional and structural model of the chip based on the microarchitecture specification, designing software tools for use with the chip based on the architecture specification, and designing chip verification tools based on the microarchitecture specification. The activities associated with chip development are divided into phases which may be performed concurrently. The result of the development is an RTL model of the chip which can be utilized in implementation of products without comprising proprietary circuit, layout and fabrication process information of the entity that is implementing the products.

Abstract: A cache has an address bus for receiving requests for data from a processor and a data bus for providing the requested data to the processor. As part of the mechanism for determining if there is a hit in the cache, the cache has TAG locations for storing TAG addresses. The hit signal is not generated unless a TAG address corresponds to the address received on the address bus. Associated with each TAG location are valid bits, disable bits, and LRU bits. The requested data is contained in data locations in the cache. Each data location has a corresponding TAG location. The disable bits can be set under the control of the processor for the case where a data location is defective. Additionally, in various diagnostic modes, the TAG locations, the valid bits, the LRU bits, and the data locations are directly accessible via the data bus.