Patents by Inventor Elie Torbey

Elie Torbey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7814386
    Abstract: A test system in an integrated circuit includes at least one boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes test logic configured to provide a test completion signal indicative of completion of a respective test based on a comparison of an output of the first storage element relative to test value (TVALUE). The output of the first storage element is provided to the input of the second storage element unchanged during a first operating state and, depending on the test completion signal, an inverted version of the output of the first storage element can be provided to the input of the second storage element during a second operating state. A bi-directional element is connected to receive the output of the second storage element and to feed the output of the second storage element back to an input of the first storage element.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: October 12, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: John Joseph Seibold, Vinay B. Jayaram, Elie Torbey
  • Publication number: 20090113264
    Abstract: A test system in an integrated circuit includes at least one boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes test logic configured to provide a test completion signal indicative of completion of a respective test based on a comparison of an output of the first storage element relative to test value (TVALUE). The output of the first storage element is provided to the input of the second storage element unchanged during a first operating state and, depending on the test completion signal, an inverted version of the output of the first storage element can be provided to the input of the second storage element during a second operating state. A bi-directional element is connected to receive the output of the second storage element and to feed the output of the second storage element back to an input of the first storage element.
    Type: Application
    Filed: May 8, 2008
    Publication date: April 30, 2009
    Inventors: JOHN Joseph SEIBOLD, Vinay B. Jayaram, Elie Torbey
  • Patent number: 6285172
    Abstract: A digital phase-locked loop (DPLL) (22) for use in one or more integrated circuits (20) that may be combined within an electronic system is disclosed. The DPLL (22) includes a phase detector (30) that generates a shift clock and a shift direction signal responsive to a phase difference between a system clock and a feedback clock. The shift direction signal is stored in a latch (32), applied to one input of an exclusive-NOR gate (34), and to shift direction inputs (R/{overscore (L)}) of first and second digital delay lines (38, 42). The first digital delay line (38) receives the system clock and generates a delayed clock that is distributed within the integrated circuit (20) by clock distribution circuitry, and that is applied to an input of the second digital delay line (42); the second digital delay line (42) generates the feedback clock that is received by the phase detector (30).
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: September 4, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Elie Torbey