Abstract: Techniques are described herein that can be used to moderate the rate at which interrupts are emitted. A network component includes the capability to issue interrupts in response to receipt of network protocol units designated as regular and high priority or in response to other causes. High priority interrupts may be accumulated. A number of accumulated high priority interrupts may be decremented each time either a regular or high priority interrupt is transferred. Addition to a number of accumulated high priority interrupts may occur at a higher rate than a rate of availability of regular priority interrupts. A counter may be used to make regular priority interrupts available. The counter may be reset each time a high priority interrupt is provided.

Abstract: A method including managing downloading of at least two firmware functions, which are accessible by more than one driver, with one processor.

Abstract: A request is received from a first requester to write a second indicator that includes an identifier of the first requester to a first indicator that indicates if a component is available. In response it is determined whether the component is available. If the component is available, the first indicator is replaced with the second indicator reducing access to the component and permitting access to the component by the first requester.

Abstract: A method, device and system for using a first verification algorithm or program to evaluate the integrity or authenticity of a second verification program. The first verification program may be stored in a device and may compare a result of such evaluation with a stored expected result. The second verification program may be included in for example an attachable memory unit of the device or other for example add-on memory unit of the device. The second verification program may evaluate the authenticity or integrity of firmware, software, data or other code that is included on the attachable device or elsewhere in the device. If both verification programs confirm the integrity of the respective codes, the firmware or software may be executed or loaded for execution by the device.

Abstract: A system including at least two processing units embedded on a chip able to communicate with each other and to generally independently control access to data from memory on the chip.

Abstract: According to some embodiments, time information is associated with data received at a digital signal processor based physical layer processing unit.

Abstract: A method, system, and apparatus to schedule commands based on a status information of a plurality of memory banks.

Abstract: In response to a requester's execution of a first operation on a storage area containing a first indicator allowing at least one requester to access the component, the storage area changes the first indicator to a second indicator reducing by one a number of requesters that can access the component. Upon completion of access, the requester executes a second operation to replace the second indicator with a third indicator allowing access to an additional requester.

Abstract: A system including at least two processing units embedded on a chip able to communicate with each other and to generally independently control access to data from memory on the chip.

Abstract: A method including managing downloading of at least two firmware functions, which are accessible by more than one driver, with one processor.

Abstract: A memory is organized into both rows and columns, and includes a write access circuit connected to the memory cells in a row-wise manner and a read access circuit connected to the memory cells in column-wise manner.