Patents by Inventor Eliezer Zand

Eliezer Zand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8020067
    Abstract: A method for locating an end of a received frame includes providing hypothetical trellis paths that end at different possible end points, performing a CRC check for each hypothetical trellis path, calculating a false detection variable for hypothetical trellis paths that passed the CRC check, and determining the end point of the received frame in response to the calculations.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: September 13, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dov Levenglick, Ron Bercovich, Eliezer Zand
  • Publication number: 20100107035
    Abstract: A device (100) for locating an end of a received frame, the device comprises: at least one memory unit (120) for storing path metrics; at least one processor, adapted to: provide hypothetical trellis paths that end at different possible end points; perform, for each hypothetical trellis path, a forward detection check; calculate a false detection variable for hypothetical trellis paths that passed the forward check; and determine the end point of the received frame in response to the calculations. Wherein the calculation of the forward detection check is much faster than the calculation of the false detection variable.
    Type: Application
    Filed: December 13, 2004
    Publication date: April 29, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Dov Levenglick, Ron Bercovich, Eliezer Zand
  • Patent number: 5628026
    Abstract: To execute a three-dimensional DMA transfer, a transfer counter register (76), which is partitioned into three sections, is loaded with initial counter values. Each section of the counter register (76) is independently controlled by a counter (72, 73, 74). Data is transferred from consecutive generated addresses for a first predetermined number of times as determined by the value in the first section of the counter register (76). An offset value is then added to a last generated address. The process is repeated for a second predetermined number of times. Then another offset value is added to the generated address. This entire process is repeated for a given number of times as determined by the third section of the register (76). The initial counter values are reloaded into counter register (76) from a backup register (77), insuring that a DMA controller (80) is ready if a new transfer request requires the same counter values as the previous transfer.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: May 6, 1997
    Assignee: Motorola, Inc.
    Inventors: Natan Baron, Eliezer Zand, Oded Norman, Zvika Rozenshein, Elchanan Rushinek