Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.