Patents by Inventor Elijah Karpov

Elijah Karpov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210296231
    Abstract: Integrated circuitry comprising devices electrically coupled through a plurality of interconnect levels in which lines of a first and second interconnect level are coupled through a planar slab via. An interconnect line may include a horizontal line segment within one of the first or second interconnect levels, and the slab via may be a vertical line segment between the first and second interconnect levels. A planar slab via may comprise one or more layers of conductive material, which have been deposited upon a planarized substrate material that lacks any features that the conductive material must fill. A planar slab via may be subtractively defined concurrently with a horizontal line of one or both of the first or second interconnect levels.
    Type: Application
    Filed: March 19, 2020
    Publication date: September 23, 2021
    Applicant: Intel Corporation
    Inventors: Elijah Karpov, Manish Chandhok, Nafees Kabir
  • Publication number: 20200388753
    Abstract: Embodiments disclosed herein include memory bitcells and methods of forming such memory bitcells. In an embodiment, the memory bitcell is part of an embedded DRAM (eDRAM) memory device. In an embodiment, the memory bitcell comprises a substrate and a storage element embedded in the substrate. In an embodiment, the storage element comprises a phase changing material that comprises a binary alloy. In an embodiment, the memory bitcell further comprises a first electrode over a first surface of the storage element, and a second electrode over a second surface of the storage element.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 10, 2020
    Inventors: Elijah KARPOV, Mauro KOBRINSKY
  • Publication number: 20200388711
    Abstract: Transistor structures with a deposited channel semiconductor material may have a vertical structure that includes a gate dielectric material that is localized to a sidewall of a gate electrode material layer. With localized gate dielectric material threshold voltage variation across a plurality of vertical transistor structures, such as a NAND flash memtory string, may be reduced. A via may be formed through a material stack, exposing a sidewall of the gate electrode material layer and sidewalls of the dielectric material layers. A sidewall of the gate electrode material layer may be recessed selectively from the sidewalls of the dielectric material layers. A gate dielectric material, such as a ferroelectric material, may be selectively deposited upon the recessed gate electrode material layer, for example at least partially backfilling the recess. A semiconductor material may be deposited on sidewalls of the dielectric material layers and on the localized gate dielectric material.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Inventors: Brian Doyle, Rami Hourani, Elijah Karpov, Prashant Majhi, Ravi Pillarisetty, Abhishek Sharma
  • Publication number: 20200303381
    Abstract: Embodiments herein describe techniques for a semiconductor device including a SRAM device having multiple SRAM memory cells, and a capacitor coupled to the SRAM device. The capacitor includes a first plate, a second plate, and a capacitor dielectric layer between the first plate and the second plate. The capacitor is to supply power to the multiple SRAM memory cells of the SRAM device in parallel for a period of time. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 24, 2020
    Inventors: Elijah KARPOV, Brian DOYLE, Abhishek SHARMA, Prashant MAJHI, Pulkit JAIN
  • Publication number: 20200235244
    Abstract: Low resistance field-effect transistors and methods of manufacturing the same are disclosed herein. An example field-effect transistor disclosed herein includes a substrate and a stack above the substrate. The stack includes an insulator and a gate electrode. The example field-effect transistor includes a semiconductor material layer in a cavity in the stack. In the example field-effect transistor, a region of the semiconductor material layer proximate to the insulator is doped with a material of the insulator.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Brian Doyle, Abhishek Sharma, Elijah Karpov, Ravi Pillarisetty, Prashant Majhi
  • Publication number: 20200203432
    Abstract: Embodiments herein describe techniques for a semiconductor device including a semiconductor substrate, a first device of a first wafer, and a second device at back end of a second wafer, where the first device is bonded with the second device. A first metal electrode of the first device within a first dielectric layer is coupled to an n-type oxide TFT having a channel layer that includes an oxide semiconductor material. A second metal electrode of the second device within a second dielectric layer is coupled to p-type organic TFT having a channel layer that includes an organic material. The first dielectric layer is bonded to the second dielectric layer, and the first metal electrode is bonded to the second metal electrode. The n-type oxide TFT and the p-type organic TFT form a symmetrical pair of transistors of a CMOS circuit. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Willy RACHMADY, Prashant MAJHI, Ravi PILLARISETTY, Elijah KARPOV, Brian DOYLE, Anup PANCHOLI, Abhishek SHARMA
  • Publication number: 20200105788
    Abstract: A transistor is disclosed. The transistor includes a p-type region, an intrinsic region coupled to the p-type region, an n-type region coupled to the intrinsic region, and a gate electrode above the intrinsic region. The ferroelectric material is on a bottom, a first side and a second side of the gate electrode, and above the intrinsic region.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Inventors: Prashant MAJHI, Brian DOYLE, Ravi PILLARISETTY, Abhishek SHARMA, Elijah KARPOV
  • Publication number: 20200105834
    Abstract: A memory cell is disclosed. The memory cell includes a word line contact, a cylindrical electrode having a top region and a bottom region, and RRAM material covering the surface of the cylindrical electrode from the top region to the bottom region. A select transistor contact is coupled to the bottom region of the cylindrical electrode.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Brian DOYLE, Prashant MAJHI, Elijah KARPOV, Ravi PILLARISETTY, Ashishek SHARMA
  • Publication number: 20200091274
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a gate dielectric layer adjacent to the channel layer, and a gate electrode separated from the channel layer by the gate dielectric layer. The gate dielectric layer includes a non-linear gate dielectric material. The gate electrode, the channel layer, and the gate dielectric layer form a non-linear capacitor. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: Abhishek SHARMA, Ravi PILLARISETTY, Brian DOYLE, Elijah KARPOV, Prashant MAJHI, Gilbert DEWEY, Benjamin CHU-KUNG, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI
  • Patent number: 8385100
    Abstract: Embodiments of apparatus and methods for an energy efficient set write of phase change memory with switch are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: February 26, 2013
    Assignee: Intel Corporation
    Inventors: Derchang Kau, Johannes Kalb, Elijah Karpov, Gianpaolo Spadini
  • Publication number: 20110134685
    Abstract: Embodiments of apparatus and methods for an energy efficient set write of phase change memory with switch are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 9, 2011
    Inventors: Derchang Kau, Johannes Kalb, Elijah Karpov, Gianpaolo Spadini
  • Patent number: 5892223
    Abstract: A multilayer microtip probe, and method of manufacture, having a microtip prepared for adhesion of a first overlayer for determining probe operating properties and a hardened protective overlayer for improving resistance to erosion and wear during probe use.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: April 6, 1999
    Assignee: Harris Corporation
    Inventors: Elijah Karpov, Jack Linn, Richard Belcher