Abstract: Systems, devices and methods are disclosed for an ultra-wide-band (UWB) transmitter tag capable of operating in different power mode depending on voltage level and/or host interruption signal. The transmitter tag comprises a power management circuit, a one-time-programmable memory (OTP), a read/write memory, a state machine for controlling/monitoring the operation of the tag. The tag goes into the high power mode when the power supply ramps up to a preset voltage level. During the high power mode, the tag consumes the higher level of electrical current as indicated by the battery current signal. Upon completion of high power consumption activity, such as OTP memory download, the tag exits the high power mode and enters the low power mode. The power supply current goes to the low level to minimize the power consumption by the tag.

Abstract: Systems, devices and methods are disclosed for an ultra-wide-band (UWB) transmitter tag capable of operating in different power mode depending on voltage level and/or host interruption signal. The transmitter tag comprises a power management circuit, a one-time-programmable memory (OTP), a read/write memory, a state machine for controlling/monitoring the operation of the tag. The tag goes into the high power mode when the power supply ramps up to a preset voltage level. During the high power mode, the tag consumes the higher level of electrical current as indicated by the battery current signal. Upon completion of high power consumption activity, such as OTP memory download, the tag exits the high power mode and enters the low power mode. The power supply current goes to the low level to minimize the power consumption by the tag.

Abstract: A FFT module for a baseband processor of a receiver includes an input for receiving a timing window correction signal. In response to the timing window correction signal the FFT module adjusts a timing window for processing groups of samples within an input queue of the FFT module.

Abstract: An apparatus, system, and method are described for synchronously resetting logic circuits. A synchronous reset signal is coupled to at least one asynchronous reset input for synchronously resetting sequential logic. In one embodiment, reset logic generates a signal coupled to the at least one asynchronous reset input of the sequential logic to synchronously reset the sequential logic.