Patents by Inventor Elio Guidetti
Elio Guidetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10935444Abstract: A stress sensor formed by a membrane plate; a first bonding region arranged on top of the membrane plate; a cover plate arranged on top of the first bonding region, the first bonding region bonding the membrane plate to the cover plate; three-dimensional piezoresistive elements extending across the membrane plate that are embedded in the bonding layer; and planar piezoresistive elements that extend across the membrane plate and are surrounded by and separated from the bonding layer.Type: GrantFiled: April 19, 2018Date of Patent: March 2, 2021Assignee: STMICROELECTRONICS S.r.l.Inventors: Elio Guidetti, Mohammad Abbasi Gavarti, Daniele Caltabiano, Gabriele Bertagnoli
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Patent number: 10914647Abstract: A capacitive sensor for monitoring stresses acting in a construction structure and having a multi-layer structure provided with an upper conductive layer defining an upper outer surface of the sensor. A lower conductive layer defines a lower outer surface. At least a first structural layer of insulating material is in contact with the upper conductive layer and at least a second structural layer of insulating material is in contact with the lower conductive layer. At least a first plate layer of conductive material and at least a second plate layer, of conductive material, and at least one dielectric layer is interposed between the first plate layer and the second plate layer to define at least one detection capacitor inside the multi-layer structure of the sensor. The upper and lower conductive layers jointly defining an electromagnetic screen for screening the detection capacitor against electromagnetic interference originating from outside the capacitive sensor.Type: GrantFiled: June 29, 2018Date of Patent: February 9, 2021Assignee: STMicroelectronics S.r.l.Inventors: Francesco Pappalardo, Agatino Pennisi, Elio Guidetti, Angelo Doriani
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Publication number: 20190011320Abstract: A capacitive sensor for monitoring stresses acting in a construction structure and having a multi-layer structure provided with an upper conductive layer defining an upper outer surface of the sensor. A lower conductive layer defines a lower outer surface. At least a first structural layer of insulating material is in contact with the upper conductive layer and at least a second structural layer of insulating material is in contact with the lower conductive layer. At least a first plate layer of conductive material and at least a second plate layer, of conductive material, and at least one dielectric layer is interposed between the first plate layer and the second plate layer to define at least one detection capacitor inside the multi-layer structure of the sensor. The upper and lower conductive layers jointly defining an electromagnetic screen for screening the detection capacitor against electromagnetic interference originating from outside the capacitive sensor.Type: ApplicationFiled: June 29, 2018Publication date: January 10, 2019Inventors: Francesco Pappalardo, Agatino Pennisi, Elio Guidetti, Angelo Doriani
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Publication number: 20180306656Abstract: A stress sensor formed by a membrane plate; a first bonding region arranged on top of the membrane plate; a cover plate arranged on top of the first bonding region, the first bonding region bonding the membrane plate to the cover plate; three-dimensional piezoresistive elements extending across the membrane plate that are embedded in the bonding layer; and planar piezoresistive elements that extend across the membrane plate and are surrounded by and separated from the bonding layer.Type: ApplicationFiled: April 19, 2018Publication date: October 25, 2018Inventors: Elio GUIDETTI, Mohammad ABBASI GAVARTI, Daniele CALTABIANO, Gabriele BERTAGNOLI
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Publication number: 20180189229Abstract: Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.Type: ApplicationFiled: February 2, 2017Publication date: July 5, 2018Inventors: Giuseppe DESOLI, Thomas BOESCH, Nitin CHAWLA, Surinder Pal SINGH, Elio GUIDETTI, Fabio Giuseppe DE AMBROGGI, Tommaso MAJO, Paolo Sergio ZAMBOTTI
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Patent number: 9424033Abstract: Apparatus and method for a modified, balanced throughput data-path architecture is given for efficiently implementing the digital signal processing algorithms of filtering, convolution and correlation in computer hardware, in which both data and coefficient buffers can be implemented as sliding windows. This architecture uses a multiplexer and a data path branch from the Address Generator unit to the multiply-accumulate execution unit. By selecting between the data path of Address Generator to execution unit and the data path of register to execution unit, the unbalanced throughput and multiply-accumulate bubble cycles caused by misaligned addressing on coefficients can be overcome. The modified balanced throughput data-path architecture can achieve a high multiply-accumulate operation rate per cycle in implementing digital signal processing algorithms.Type: GrantFiled: July 8, 2013Date of Patent: August 23, 2016Assignees: STMICROELECTRONICS (BEIJING) R&D COMPANY LTD., STMICROELECTRONICS S.R.L.Inventors: PengFei Zhu, HongXia Sun, YongQiang Wu, Elio Guidetti
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Patent number: 9378077Abstract: Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.Type: GrantFiled: August 4, 2010Date of Patent: June 28, 2016Assignee: STMICROELECTRONICS S.R.L.Inventors: Francesco Pappalardo, Giuseppe Notarangelo, Elio Guidetti
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Patent number: 9082476Abstract: An apparatus and method are disclosed to implement digital signal processing operations involving multiply-accumulate (MAC) operations, by using a modified balanced data structure and accessing architecture. This architecture maintains a data-path connecting one address generation unit, one register file and one MAC execution unit. The register file has a hierarchical grouping organization of individual registers, which reduces bubble cycles caused by memory misalignments. This architecture uses parallel execution and can achieve two or more MAC operations per cycle.Type: GrantFiled: July 8, 2013Date of Patent: July 14, 2015Assignees: STMICROELECTRONICS (BEIJING) R&D COMPANY LTD., STMICROELECTRONICS S.R.L.Inventors: PengFei Zhu, HongXia Sun, YongQiang Wu, Elio Guidetti
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Patent number: 9015377Abstract: A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports.Type: GrantFiled: December 3, 2012Date of Patent: April 21, 2015Assignees: STMicroelectronics (Bejing) R&D Company Ltd., STMicroelectronics S.R.L.Inventors: YongQiang Wu, PengFei Zhu, HongXia Sun, Elio Guidetti
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Publication number: 20140019679Abstract: An apparatus and method are disclosed to implement digital signal processing operations involving multiply-accumulate (MAC) operations, by using a modified balanced data structure and accessing architecture. This architecture maintains a data-path connecting one address generation unit, one register file and one MAC execution unit. The register file has a hierarchical grouping organization of individual registers, which reduces bubble cycles caused by memory misalignments. This architecture uses parallel execution and can achieve two or more MAC operations per cycle.Type: ApplicationFiled: July 8, 2013Publication date: January 16, 2014Inventors: PengFei Zhu, HongXia Sun, YongQiang Wu, Elio Guidetti
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Publication number: 20140019727Abstract: Apparatus and method for a modified, balanced throughput data-path architecture is given for efficiently implementing the digital signal processing algorithms of filtering, convolution and correlation in computer hardware, in which both data and coefficient buffers can be implemented as sliding windows. This architecture uses a multiplexer and a data path branch from the Address Generator unit to the multiply-accumulate execution unit. By selecting between the data path of Address Generator to execution unit and the data path of register to execution unit, the unbalanced throughput and multiply-accumulate bubble cycles caused by misaligned addressing on coefficients can be overcome. The modified balanced throughput data-path architecture can achieve a high multiply-accumulate operation rate per cycle in implementing digital signal processing algorithms.Type: ApplicationFiled: July 8, 2013Publication date: January 16, 2014Inventors: PengFei ZHU, HongXia SUN, YongQiang WU, Elio GUIDETTI
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Patent number: 8078804Abstract: A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.Type: GrantFiled: June 26, 2007Date of Patent: December 13, 2011Assignees: STMicroelectronics S.r.l., STMicroelectronics N.V.Inventors: Francesco Pappalardo, Giuseppe Notarangelo, Elena Salurso, Elio Guidetti
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Patent number: 8060725Abstract: A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) function. A load unit loads into the processor clusters data to be processed according to a same instruction. An intercluster data path exchanges data between the processor clusters. The intercluster data path is scalable to activate selected processor clusters. The processor operates simultaneously on SIMD, scalar and vectorial data.Type: GrantFiled: June 26, 2007Date of Patent: November 15, 2011Assignees: STMicroelectronics S.R.L., STMicroelectronics N.V.Inventors: Francesco Pappalardo, Giuseppe Notarangelo, Elena Salurso, Elio Guidetti
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Publication number: 20110060975Abstract: Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.Type: ApplicationFiled: August 4, 2010Publication date: March 10, 2011Applicant: STMICROELECTRONICS s.r.l.Inventors: Francesco PAPPALARDO, Giuseppe Notarangelo, Elio Guidetti
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Patent number: 7831804Abstract: A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. Additionally the processor architecture of the present invention enable dynamic switching between instruction parallelism and data parallel processing typical of vectorial functionality. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.Type: GrantFiled: May 30, 2008Date of Patent: November 9, 2010Assignee: ST Microelectronics S.R.L.Inventors: Francesco Pappalardo, Giuseppe Notarangelo, Elio Guidetti
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Publication number: 20080294871Abstract: A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. Additionally the processor architecture of the present invention enable dynamic switching between instruction parallelism and data parallel processing typical of vectorial functionality. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.Type: ApplicationFiled: May 30, 2008Publication date: November 27, 2008Applicant: STMICROELECTRONICS S.R.L.Inventors: Francesco Pappalardo, Giuseppe Notarangelo, Elio Guidetti
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Publication number: 20080016317Abstract: A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.Type: ApplicationFiled: June 26, 2007Publication date: January 17, 2008Applicants: STMicroelectronics S.r.l., STMicroelectronics N.V.Inventors: Francesco Pappalardo, Giuseppe Notarangelo, Elena Salurso, Elio Guidetti
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Publication number: 20080016319Abstract: A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) function. A load unit loads into the processor clusters data to be processed according to a same instruction. An intercluster data path exchanges data between the processor clusters. The intercluster data path is scalable to activate selected processor clusters. The processor operates simultaneously on SIMD, scalar and vectorial data.Type: ApplicationFiled: June 26, 2007Publication date: January 17, 2008Applicants: STMicroelectronics S.r.l., STMicroelectronics N.V.Inventors: Francesco Pappalardo, Giuseppe Notarangelo, Elena Salurso, Elio Guidetti